AM2434: AM243x: Loading code into PSRAM from M4F does not work

Andreas Zeiler

Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

Hi,

is it possible to load (or even access) memory in PSRAM when connected to M4F?

I'm trying to place some code in our PSRAM (Address 0x50000000) but CCS says the following:

BLAZAR_Cortex_M4F_0: File Loader: Verification failed: Values at address 0x503FC000 do not match Please verify target memory and memory map.

Looking at the map File from the Linker, I see the correct section and that the code was place there.

I can load a fw image for R5 which contains code in PSRAM. But on M4F it does not work.

MPU on R5 is configured as Supervisor RD+WR, User RD+WR, cached, exec allowed. So even debugger should not have any problems placing code in there.

I also configured MPU of M4F to the same values (but only these 16kB block).

Kind regards

Andreas

over 3 years ago

0 Ming Wei over 3 years ago

TI__Mastermind 49255 points

Hi Andreas,

I am still checking with the system team and AVV team on whether the M4F core can access to the GPMC interface directly. From the AM243x TRM, it seems not possible. Will give confirmation by tomorrow.

Best regards,

Ming

+1 Ming Wei over 3 years ago in reply to Ming Wei

TI__Mastermind 49255 points

Hi Andreas,

I have asked our system expert. The answer is that by default the M4F core can access to GPMC CFG MMR and its address space (0x50000000). It is indicated in the Table 5-1198. MCU PSC Information in AM243x TRM: LPSC_MCU2MAIN(4) ON is the default state.

My guess is that if you connect to the R5F0_0 first, then connect the M4F, you should be able to load the program to 0x50000000.

The reason is that the GPMC needs to be set up before you can access it. The gel file for R5F0_0 will set up the GPMC for you, but the gel file for M4F does not.

Please let me know how it comes out.

Best regards,

Ming

0 Andreas Zeiler over 3 years ago in reply to Ming Wei

Intellectual 600 points

Hi Ming,

the GPMC is setup, as we already have in in the bootloader.

I don't use any GEL scripts to setup the soc. It is all done by the bootloader. When loading firmware, I just connect to R5 and M4, reset the core and load a new firmware into the core.

But I will check the configuration registers.

Kind regards

Andreas

0 Ming Wei over 3 years ago in reply to Andreas Zeiler

TI__Mastermind 49255 points

Hi Andreas,

Please keep us updated on this issue.

Best regards,

Ming

0 Andreas Zeiler over 3 years ago in reply to Ming Wei

Intellectual 600 points

Hi,

sorry klicked on wrong button...

I cannot find the address of LPSC_MCU2MAIN.

Whats the address???

0 Ming Wei over 3 years ago in reply to Andreas Zeiler

TI__Mastermind 49255 points

Hi Andreas,

Please check out the gel file for AM64x in CCS: C:\ti\ccs1120\ccs\ccs_base\emulation\gel\AM64x\AM64_PSC\AM64_PSC.gel. There is a function which gets the MCU PSC state: Get_MCU_PSC_State( unsigned int pd_id, unsigned int md_id ).

Best regards,

Ming

0 Andreas Zeiler over 3 years ago in reply to Ming Wei

Intellectual 600 points

Hi,

don't know if thats right but here is the output. I used the PSC Gel file for AM243x and selected Scripts > Power Sleep Controller > Common PSC Power Controls > Get PSC All States:

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BLAZAR_Cortex_M4F_0: GEL Output: Getting all PSC power states in progress... 
BLAZAR_Cortex_M4F_0: GEL Output: Getting all MAIN PSC peripheral states in progress......
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_MAIN_ALWAYSON
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_MAIN_TEST
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_MAIN_PBIST
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_DMSC
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_EMMC_4B
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_EMMC_8B
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_USB
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

BLAZAR_Cortex_M4F_0: GEL Output: Getting all PSC power states in progress... 
BLAZAR_Cortex_M4F_0: GEL Output: Getting all MAIN PSC peripheral states in progress......
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_MAIN_ALWAYSON
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_MAIN_TEST
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_MAIN_PBIST
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_DMSC
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_EMMC_4B
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_EMMC_8B
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_USB
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_ADC
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_GPMC
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_EMIF_CFG
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_EMIF_DATA
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_MCAN_0
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_MCAN_1
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_SA2UL
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_SERDES_0
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_PCIE_0
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_PULSAR_0_R5_0
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_PULSAR_0_R5_1
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_PULSAR_PBIST_0
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: SyncResetDisable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_PULSAR_1_R5_0
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_PULSAR_1_R5_1
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_PULSAR_PBIST_1
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: SyncResetDisable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_ICSSG_0
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_ICSSG_1
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_DEBUGSS
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_CPSW3G
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: SyncResetDisable
BLAZAR_Cortex_M4F_0: GEL Output: Getting the state of all MAIN peripherals done. 
BLAZAR_Cortex_M4F_0: GEL Output: Getting all MCU peripheral states in progress......
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_MCU_ALWAYSON
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_TEST
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: SyncResetDisable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_MAIN2MCU
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_MCU2MAIN
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: State of LPSC_M4F
BLAZAR_Cortex_M4F_0: GEL Output: Power Domain: On
BLAZAR_Cortex_M4F_0: GEL Output: Module State: Enable
BLAZAR_Cortex_M4F_0: GEL Output: Getting the state of all MCU peripherals done. 
BLAZAR_Cortex_M4F_0: GEL Output: Getting all PSC power states done.

Seems the bit you mentioned is active. As already said, we're using PSRAM for R5F Core. R5 Core is able to access it and run code. But I cannot access PSRAM from M4F.

Here is my RAT Region config for M4F:

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AddrTranslateP_RegionConfig gAddrTranslateRegionConfig[CONFIG_ADDR_TRANSLATE_REGIONS] = 
{
    {
        .localAddr = 0x80000000u,
        .systemAddr = 0x0u,
        .size = AddrTranslateP_RegionSize_512M,
    },
    {
        .localAddr = 0xA0000000u,
        .systemAddr = 0x20000000u,
        .size = AddrTranslateP_RegionSize_512M,
    },
    {
        .localAddr = 0xC0000000u,
        .systemAddr = 0x40000000u,
        .size = AddrTranslateP_RegionSize_512M,
    },
    {
        .localAddr = 0x60000000u,
        .systemAddr = 0x60000000u,
        .size = AddrTranslateP_RegionSize_512M,
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

AddrTranslateP_RegionConfig gAddrTranslateRegionConfig[CONFIG_ADDR_TRANSLATE_REGIONS] = 
{
    {
        .localAddr = 0x80000000u,
        .systemAddr = 0x0u,
        .size = AddrTranslateP_RegionSize_512M,
    },
    {
        .localAddr = 0xA0000000u,
        .systemAddr = 0x20000000u,
        .size = AddrTranslateP_RegionSize_512M,
    },
    {
        .localAddr = 0xC0000000u,
        .systemAddr = 0x40000000u,
        .size = AddrTranslateP_RegionSize_512M,
    },
    {
        .localAddr = 0x60000000u,
        .systemAddr = 0x60000000u,
        .size = AddrTranslateP_RegionSize_512M,
    },
};

Do I need to setup something else? I don't think bootloader is setting or resetting something here.

Kind regards

Andreas

0 Ming Wei over 3 years ago in reply to Andreas Zeiler

TI__Mastermind 49255 points

Hi Andreas,

Looks like the GPMC0_DATA (0x50000000, 128MB) is not defined in the RAT. That might be the problem.

Best regards,

Ming

0 Andreas Zeiler over 3 years ago in reply to Ming Wei

Intellectual 600 points

Hi Ming,

GPMC Section is defined in R5 SysConfig file with following values:

- Supervisor R/W, User R/W

- Cached

-Execution allowed

I assume, after loading at least R5 and before code runs to main, it initializes MPU Config. So this section should be marked as R/W for R5.

Assuming that loading M4 Code (with sections in PSRAM) it should work. Even if MPU Config in M4F Core is invalid or prohibit into this area.

Also I added a 16kB Section in PSRAM for placing a symbol of M4F into PSRAM. At time of downloading M4F Image to the SoC (M4F) Debugger is not able to access PSRAM. But from R5 Core it is working because PSRAM is initialized.

Also I added RAT Region 0x50000000 to 0x50000000. No success here.

Bootloader runs on R5. So this should be also no problem, because R5 Firmware already initialized this area again.

Kind regards

Andreas

0 Ming Wei over 3 years ago in reply to Andreas Zeiler

TI__Mastermind 49255 points

Hi Andreas,

I saw all the M4F core example have their own MPU and RAT settings. Can you add the 0x50000000 to the M4F MPU too?

Best regards,

Ming

0 Andreas Zeiler over 3 years ago in reply to Ming Wei

Intellectual 600 points

Hi Ming,

I already added this section in RAT as mentioned in my last post. But this is not the source of this problem, as M4 code starts after uploading it to the core, which is the main problem here. I cannot download the code because debugger has no access to PSRAM.

regards

Andreas

0 Ming Wei over 3 years ago in reply to Andreas Zeiler

TI__Mastermind 49255 points

Hi Andreas,

in the example.syscfg file of the M4F CCS project, there are both RAT and MPU settings. You have add 0x50000000 for both RAT and MPU.

Best regards,

Ming

0 Andreas Zeiler over 3 years ago in reply to Ming Wei

Intellectual 600 points

Hi,

yes added this. No success.

Regards

Andreas

0 Ming Wei over 3 years ago in reply to Andreas Zeiler

TI__Mastermind 49255 points

Hi Andreas,

Can you share your example.syscfg file with us?

Best regards,

Ming

0 Benjamin Scheufele over 3 years ago in reply to Ming Wei

Intellectual 360 points

Hey Ming,

Our RAT configuration causes this problem. We need to map the local address for the PSRAM to the range 0x62000000 (see Table 2-5. MCU_M4FSS0 Memory Map), directly after the flash mapping. With the correct mapping, we have access to the entire PSRAM and can see the memory in the memory browser of the ccs.

RAT config for 32 MByte Flash: