RM46L852: Inconsistent GIO interrupt latency

Fred Knud

Part Number: RM46L852

Hello TI,

We have been working with the RM46 for a timing-critical application and are using GIOA[6]/[7] as inputs to trigger its ISR gioHighLevelInterrupt().
To measure the time to enter the interrupt we are setting a pin in the interrupt routine and measuring the delay between an applied input and the pin being set.

Now, the time from trigger until the pin is set is about 1.5 μs which is fine for our application. However, it is not exactly 1.5 μs but more around 1.5 μs ± 120 ns.
We would really like to decrease that variance as much as possible, even if at cost of time to enter the routine - we are just looking for it to be as consistent as possible.
The ISR that sets the pin is set as FIQ. There are a few other FIQ interrupts, we have already tried to disable them but the issue persists.

Some solutions we have tried already:

- We have tried to run the program with all other interrupts disabled.
- We tried setting other pins inside the ISR to see if the time to set the pin was the issue.
- We tried to set high/low/either polarity on the interrupt trigger.

So the question is basically - is there anything we can do to ensure that the processor takes the same time to enter the interrupt routine every time? It does not necessarily have to be faster than it already is, just consistent.

Thanks in advance.

over 3 years ago

0 QJ Wang over 3 years ago

TI__Guru**** 198766 points

Hi Fred,

The IRQ latency for GIO interrupt is around 45 CPU clock cycles. The latency is also dependent on the state of the CPU when the interrupt is requested. For example, if the CPU is reading from memory with wait states it would need to wait for this read to complete before it jumps to the interrupt service routine.

You can enable IRQ to use the CPU's VIC port, and leave the FIQ for other more important INT such as ESM.

0 Chester Gillon over 3 years ago

Guru 92251 points

Fred Knud said:
We have been working with the RM46 for a timing-critical application and are using GIOA[6]/[7] as inputs to trigger its ISR gioHighLevelInterrupt().

From a quick look at the datasheet the pins for GIOA[6] and GIOA[7] can also be muxed for the Enhanced High-End Timer Modules (N2HET).

Could the N2HET be used to help your timing-critical application?

0 Fred Knud over 3 years ago in reply to Chester Gillon

Prodigy 10 points

Hi Chester,
We had been looking into the N2HET earlier but decided to go with the RTI module instead. However, after your answer and after reading other timing-related topics I decided to give the N2HET another go and it worked! The interrupt fires with only a couple of ns variance.
Switching from using the GIO module to trigger the interrupt to using the N2HET module solved the issue.

For anyone else who might stumble upon this post, I based my solution on this post:
https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/759153/rm46l852-n2het-as-gio-interrupts

Thanks for taking the time to reply!

0 Fred Knud over 3 years ago in reply to QJ Wang

Prodigy 10 points

Hi QJ, thanks for the quick reply.
After reading your answer, I tried to use the VIC port instead but either I did not implement it properly or it was not working. At any rate, I did not see an improvement to the interrupt firing time consistency. In the end, I ended up using the N2HET module to fire the interrupt instead which solved the issue.

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RM46L852: Inconsistent GIO interrupt latency