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AM2634-Q1: How to configure the priorities of different controllers accessing L3_MAIN interconnect

Will Gao
Intellectual 2335 points
Part Number: AM2634-Q1

Hi experts, 

I'd like to know how to manage the priority of TPTCs accessing L3_MAIN interconnect comparing with other bus host controllers (CPU, etc. ). In TRM, it said that " The priorities of transfer requests (read and write commands) from the EDMA transfer controllers with respect to other controllers within the device IRQ_CROSSBAR are programmed using the Control Module registers." 

But in Control Module registers manual, I could not find any information about it. So please help. 

Regards, 

Will 

  • 0
    TI__Expert 7585 points

    Hi Will

    We are looking into this. Will get back on this shortly

    Regards

    Sri Vidya

  • 0
    TI__Mastermind 29198 points

    Hi Will,

    Sorry for the delay on this. We're pursuing it and will get back with you.

    Regards,
    Frank

  • +1
    TI__Mastermind 29198 points

    Hi Will,

    The information in Section 11.2.3.11.4 Performance Considerations of the TRM (spruj17b.pdf) is incorrect. This will be corrected in a future revision of the TRM.

    The SOC follows the below master ID assignment priorities in Round Robin (lower ID assignment means higher priority). The TPTC priorities are highlighted. Note TPTC priorities are high. There aren't any SOC Control registers for configuring the priority. These priorities are fixed and part of interconnect during RTL generation.

    Regards,
    Frank

    Master interface Summary

    IP name

    Master interface

    Bridge is needed

    bus width

    protocol

    Notes

    masterID assignment

    MPU is needed or not

    R5_0

    R5_0_AXI_mst_r

    64

    VBUSM

    read only interface

    16

    N

    R5_0

    R5_0_AXI_mst_w

    64

    VBUSM

    write only interface

    17

    N

    R5_1

    R5_1_AXI_mst_r

    64

    VBUSM

    read only interface

    18

    N

    R5_1

    R5_1_AXI_mst_w

    64

    VBUSM

    write only interface

    19

    N

    R5_2

    R5_2_AXI_mst_r

    64

    VBUSM

    read only interface

    20

    N

    R5_2

    R5_2_AXI_mst_w

    64

    VBUSM

    write only interface

    21

    N

    R5_3

    R5_3_AXI_mst_r

    64

    VBUSM

    read only interface

    22

    N

    R5_3

    R5_3_AXI_mst_w

    64

    VBUSM

    write only interface

    23

    N

    HSM

    HSM_mst

    Br_P2M_HSM

    32

    VBUSP

    5

    N

    HSM

    HSM_TC0_R

    64

    VBUSM

    12

    N

    HSM

    HSM_TC0_W

    64

    VBUSM

    13

    N

    HSM

    HSM_TC1_R

    64

    VBUSM

    14

    N

    HSM

    HSM_TC1_W

    64

    VBUSM

    15

    N

    SoC

    SoC_TC0_R

    64

    VBUSM

    8

    N

    SoC

    SoC_TC0_W

    64

    VBUSM

    9

    N

    SoC

    SoC_TC1_R

    64

    VBUSM

    10

    N

    SoC

    SoC_TC1_W

    64

    VBUSM

    11

    N

    debugss

    debugss_mst

    Br_P2M_debugss

    32

    vbusp

    4

    N

    ICSSM

    ICSSM_PRU0

    32

    vbusp

    6

    N

    ICSSM

    ICSSM_PRU1

    32

    vbusp

    7

    N

     

    From SCRP_32b_CPSW

    Br_P2M_CPSW

    32

    vbusp

    28-29

    N
  • 0 in reply to Frank Livingston
    TI__Intellectual 2335 points

    Thank you! Frank. Well understood.