TMS570LC4357: API to change the CAN bit rate in Halcogen generated drivers

Harshal Pawar said:

Please let me know the procedure to change the bit rate. Do I need to enter in the initialization mode again to change the bit rate?

Yes. Entering "Initialization mode" and enabling the "configure change" are required for changing the CAN bit timing. Below is the bit timing configuration flow.

step 1: Set "Init" bit of control register. 

step 2: Set "CCE" bit in control register

step 3: Wait for the Init bit to get set

step 4: Write the Bit-Timing values into the Bit-Timing Register (BTR)

Step 5: Clear the CCE bit followed by Init bit

Step 6: Wait for the "Init" bit to clear

Harshal Pawar said:

2. How the value of following parameters is decided?

   a. Prescaler, b. Phase_Seg2, c. Phase_Seg1, d. Prop_Seg, e. Synchronization Jump Width

a. The baud rate prescaler is to determine the sampling clock period. A single period is referred to as a time quantum (Tq).

There are two prescalers: BRP (0~63) and BRPE. BRPE is BRP extension. The actual prescaler = (BRP+1) + (BRPE<<6) (refer to  CAN BTR register)

If CAN clock is 75MHz, BRP=10, and BRPE=1, then prescaler=(10+1)+ 64 = 75

Tq = BaudRate Prescaler / CAN Clock = 75 / 75 MHz = 1 us = 1000 ns

b. The CAN bit time is made up of non-overlapping segments. Each of these segments are made up of integer units called Time Quanta (Tq)

The Nominal Bit Time (t_bit) = t_SyncSeg + t_PropSeg + t_PS1 + t_PS2

The Sync_Seg is the 1st segment in the Nominal Bit Time and is used to synchronize the nodes on the bus. Bit edges are expected to occur within the SyncSeg. This segment is fixed at 1Tq.

The Prop_Seg is to compensate for physical delays between nodes. The propagation delay is defined as twice the sum of the signal’s propagation time on the bus line, including the delays associated with the bus driver.

Phase_Seg1 and Phase_Seg2 are used to compensate for edge phase errors on the bus. PS1 can be lengthened or PS2 can be shortened by re-syncronization. Phase_Seg1 acts as a buffer that can be lengthened to resynchronize with the bitstream. Phase_Seg2 is like phase segment 1, but it occurs after the sampling point instead of before. Phase_Seg2 can be shortened to resynchronize with the bit stream.

The SJW is the maximum time by which the bit sampling period may be lengthened or shortened during each cycle to adjust for oscillator mismatch between nodes.

Please use HALCOGen to calculate those parameters or use the excel spreadsheet as a reference:

CAN Bit Timing Calculator.xls

Thanks for the help.

It would be grateful if you share API to change the CAN bit rate if available.

Below is the API have written. Please let me know if I'm correct. I had taken the bit rate parameters from Halcogen. But as you mentioned "Wait for the Init bit to get set"  & "Wait for the "Init" bit to clear" how do I ensure it?

void can1UpdateBAUD_500Kb(void)
{
/* Set "Init" bit of control register */
canREG1->CTL |= (uint32) 0x00000001U;

/* Set "CCE" bit in control register */
canREG1->CTL |= (uint32) (1U << 6U);

/** - Setup bit timing for 500Kbit/s
* - Setup baud rate prescaler extension
* - Setup TSeg2
* - Setup TSeg1
* - Setup sample jump width
* - Setup baud rate prescaler
*/
canREG1->BTR = (uint32)((uint32)0U << 16U) |
(uint32)((uint32)(2U - 1U) << 12U) |
(uint32)((uint32)((3U + 2U) - 1U) << 8U) |
(uint32)((uint32)(2U - 1U) << 6U) |
(uint32)19U;

/* Clear "CCE" bit in control register */
canREG1->CTL &= ~ (uint32) (1U << 6U);

/* Clear "Init" bit of control register */
canREG1->CTL &= ~ (uint32) (1U << 0U);
}