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LP-AM243: OSPI register

Cherry Zhou
Mastermind 22235 points
Part Number: LP-AM243

Hi team,

Here's an issue from the customer may need your help:

1Ch OSPI_IND_AHB_ADDR_TRIGGER_REG Indirect trigger address register 0FC4 001Ch

24h OSPI_REMAP_ADDR_REG Address remapping register                            0FC4 0024h

80h OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG Indirect trigger address range register 0FC4 0080h

OSPI_REMAP_ADDR_REG, 0x6000_0000( it should be the memory-mapped address settings)

OSPI_IND_AHB_ADDR_TRIGGER_REG(which should be the trigger address for indirect Flash read and write)

OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG(which should be the range of address triggers when indirectly reading or writing flash)

For example, if set the memory map address to 0x6000_0000, the trigger address to 0x7000_1000, and the trigger address range to 0x1000. Then read or write 0x7000_1200, it can read or write the flash in space 0x6000_1200.

However, there is no response to setting these registers.

Below is a section of source code for the SDK:

CSL_REG32_WR(&pReg->IND_AHB_ADDR_TRIGGER_REG, 0);
CSL_REG32_WR(&pReg->INDIRECT_TRIGGER_ADDR_RANGE_REG, OSPI_utilLog2(128));

When reading or writing to Flash, only 0x6000_0000 can be read or written to operate SRAM FIFO to further enable indirect read and write functionality. Why is this?

Could you help check this case? Thanks.

Best Regards,

Cherry

  • 0
    TI__Expert 7670 points

    Hi Cherry,

    We are looking into this issue. I have a few questions as well to help us work more efficiently:

    • What flash memory is your customer using with AM243x?
    • Do you have the schematic with the connections to the Flash?
    • Could you provide a full register dump of the OSPI section during the application? 

    You can reach out offline with the information requested if you have it. Thanks.

    Best,

    Daniel

  • 0 in reply to Daniel Bermudez
    TI__Mastermind 22235 points

    Hi Daniel,

    Thanks for your support.

    Daniel Bermudez said:
    What flash memory is your customer using with AM243x?

    GD25Q128E.

    Daniel Bermudez said:
    Do you have the schematic with the connections to the Flash?

    Please see the figure below:

    Daniel Bermudez said:
    Could you provide a full register dump of the OSPI section during the application? 

    The customer mainly wants to know what do the memory-mapped address setting registers, the indirect trigger address register, and the indirect trigger address range register mean and how do they apply?

    Thanks and regards,

    Cherry

  • 0 in reply to Cherry Zhou
    TI__Expert 7670 points

    Hi Cherry,

    Descriptions of these registers and their intended functionality can be found on the TRM. Going through them we can see the following:

    OSPI_IND_AHB_ADDR_TRIGGER_REG: This register allows to define the address distinguishing DAC access from triggered INDAC one.
    When the incoming data read/write access address matches a range of addresses from this trigger address to the trigger address + [configured range in OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG]

    OSPI_REMAP_ADDR_REG: This register allows to define the address offset for DAC (Direct Access Controller) accesses. This register is used to remap an incoming data address to a different address used by the FLASH device.

    OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG: This register allows the user to define the indirect trigger address range. If the configured range exceeds number of bytes programmed for particular indirect transfer, there is no need to detect indirect trigger address boundaries by software.

    Not all of the registers are relevant for INDAC (Indirect Access Controller) mode of communication. Section 12.3.2.4.10 OSPI Indirect Access Controller (INDAC), along with its subsections 12.3.2.4.10.1 Indirect Read Controller and 12.3.2.4.10.2 Indirect Write Controller describe the process of both indirect reads and writes which contains information on what registers need to be configured to ensure correct indirect communication.

    Hope this helps!

    Best,
    Daniel

    link to the TRM: https://www.ti.com/lit/ug/spruim2d/spruim2d.pdf?ts=1665783046154&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FAM2431%253FkeyMatch%253DAM243X 

  • 0 in reply to Daniel Bermudez
    TI__Mastermind 22235 points

    Hi Daniel,

    Thank you for the detailed response!

    NorFlash has 64 MB, and configured as follows:

    OSPI_IND_AHB_ADDR_TRIGGER_REG=0x5001_0000，OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG=6，OSPI_REMAP_ADDR_REG=0x5002_0000

    How to determine if it is a DAC or an INDAC access? For example, reading and writing 0x5001_0010, 0x5000_0200, 0x5030_0400, 0x6010_1030, 0x7300_0100, 0x9500_2300, which triggers the DAC access and which triggers the INDAC access?

    What should they do if they want to write the 0x100 location of Flash?

    Thanks and regards,

    Cherry

  • 0 in reply to Cherry Zhou
    TI__Expert 7670 points

    Hi Cherry, 

    the only distinction method that exists between DAC and INDAC addresses is the fact of whether or not an address is specified in the as part of the range of addresses defined as INDAC addresses. As noted by the TRM:

     

    This means that every address will be considered a DAC address if it does not fall in the range specified by:

     OSPI_IND_AHB_ADDR_TRIGGER_REG[ADDR_FLD] + (OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG[IND_RANGE_WIDTH_FLD] - 1)

    Also, keep in mind the following: Indirect trigger address does not have any relationship with flash address. It is just to indicate that data should take SRAM as source instead of FLASH Memory array after triggering of any valid Indirect Read/Write

    The FLASH address for Indirect Read/Write is taken from the OSPI_INDIRECT_READ_XFER_START_REG/OSPI_INDIRECT_WRITE_XFER_START_REG registers.

    With this in mind, if the goal is to write to Flash address location 0x100 then this is the value that should be specified in the OSPI_INDIRECT_WRITE_XFER_START_REG register.

    The process on how to set up an indirect write is detailed in the TRM (12.3.2.4.10.2.1 Indirect Write Transfer Process) as follows:

    Best,

    Daniel

  • 0 in reply to Daniel Bermudez
    TI__Mastermind 22235 points

    Hi Daniel,

    Actual operating SDK source code, trigger address OSPI_IND_AHB_ADDR_trigger_REG=0 should be 0x6000_0000.

    Customer did the test,  OSPI_IND_AHB_ADDR_trigger_REG=0x6000_0000, OSPI_indirection_trigger_ADDR_range_REG=7, then write the data in the range 0x6000_0000 to 0x6000_0080, for example, 0x6000_0004. but failed and it must be done when OSPI_IND_AHB_ADDR_trigger_REG = 0.

    Thanks and regards,

    Cherry

  • 0 in reply to Cherry Zhou
    TI__Expert 7670 points

    Hi Cherry,

    I'm reaching out for help on this, thanks for your patience

    Best,

    Daniel

  • 0 in reply to Daniel Bermudez
    TI__Mastermind 22235 points

    Hi Daniel,

    May I know any feedback on this issue?

    Thanks and regards,

    Cherry

  • 0 in reply to Cherry Zhou
    TI__Expert 8165 points

    Hi Cherry,

    I am not quite clear on how you're 'writing' the data here. The flash memory is not byte accessible for writes, at least not completely. Usually writes are done page by page, and after writing each page you have to wait a certain amount of time specific to the flash. So can you send a diff or patch of what customer tried here? Also which version of MCU+ SDK is the customer on?

    Regards,
    Anand M