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Hi team,
Here's an issue from the customer may need your help:
1Ch OSPI_IND_AHB_ADDR_TRIGGER_REG Indirect trigger address register 0FC4 001Ch
24h OSPI_REMAP_ADDR_REG Address remapping register 0FC4 0024h
80h OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG Indirect trigger address range register 0FC4 0080h
OSPI_REMAP_ADDR_REG, 0x6000_0000( it should be the memory-mapped address settings)
OSPI_IND_AHB_ADDR_TRIGGER_REG(which should be the trigger address for indirect Flash read and write)
OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG(which should be the range of address triggers when indirectly reading or writing flash)
For example, if set the memory map address to 0x6000_0000, the trigger address to 0x7000_1000, and the trigger address range to 0x1000. Then read or write 0x7000_1200, it can read or write the flash in space 0x6000_1200.
However, there is no response to setting these registers.
Below is a section of source code for the SDK:
CSL_REG32_WR(&pReg->IND_AHB_ADDR_TRIGGER_REG, 0);
CSL_REG32_WR(&pReg->INDIRECT_TRIGGER_ADDR_RANGE_REG, OSPI_utilLog2(128));
When reading or writing to Flash, only 0x6000_0000 can be read or written to operate SRAM FIFO to further enable indirect read and write functionality. Why is this?
Could you help check this case? Thanks.
Best Regards,
Cherry
Hi Daniel,
Thanks for your support.
What flash memory is your customer using with AM243x?
GD25Q128E.
Do you have the schematic with the connections to the Flash?
Please see the figure below:
Could you provide a full register dump of the OSPI section during the application?
The customer mainly wants to know what do the memory-mapped address setting registers, the indirect trigger address register, and the indirect trigger address range register mean and how do they apply?
Thanks and regards,
Cherry
Hi Cherry,
the only distinction method that exists between DAC and INDAC addresses is the fact of whether or not an address is specified in the as part of the range of addresses defined as INDAC addresses. As noted by the TRM:
This means that every address will be considered a DAC address if it does not fall in the range specified by:
OSPI_IND_AHB_ADDR_TRIGGER_REG[ADDR_FLD] + (OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG[IND_RANGE_WIDTH_FLD] - 1)
Also, keep in mind the following: Indirect trigger address does not have any relationship with flash address. It is just to indicate that data should take SRAM as source instead of FLASH Memory array after triggering of any valid Indirect Read/Write
The FLASH address for Indirect Read/Write is taken from the OSPI_INDIRECT_READ_XFER_START_REG/OSPI_INDIRECT_WRITE_XFER_START_REG registers.
With this in mind, if the goal is to write to Flash address location 0x100 then this is the value that should be specified in the OSPI_INDIRECT_WRITE_XFER_START_REG register.
The process on how to set up an indirect write is detailed in the TRM (12.3.2.4.10.2.1 Indirect Write Transfer Process) as follows:
Best,
Daniel
Hi Daniel,
Actual operating SDK source code, trigger address OSPI_IND_AHB_ADDR_trigger_REG=0 should be 0x6000_0000.
Customer did the test, OSPI_IND_AHB_ADDR_trigger_REG=0x6000_0000, OSPI_indirection_trigger_ADDR_range_REG=7, then write the data in the range 0x6000_0000 to 0x6000_0080, for example, 0x6000_0004. but failed and it must be done when OSPI_IND_AHB_ADDR_trigger_REG = 0.
Thanks and regards,
Cherry
