LAUNCHXL2-TMS57012: GPT Autosar driver, second timer configuration is not working

Ravichandra Sereddy Thipperudra Reddy

I have configured two GPT timers as below. I see the first GPT timer 'BQ761xNw1GptChannel' is not working, i am not seeing the callback 'BQ761xNw1GptCbk()' . Kindly please check and provide your inputs

over 3 years ago

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago

TI__Intellectual 860 points

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/Gpt.xdm

0 Kowshik Gudimetla over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Genius 15435 points

Hi Ravi,

I'm working on this query, please allow me some time to check this on my end and get back to you.

Thanks,
G Kowshik

0 Kowshik Gudimetla over 3 years ago in reply to Kowshik Gudimetla

TI__Genius 15435 points

Hi Ravi,

I have re-assigned the thread to the appropriate owner (Hercules support owner).

Thanks

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to Kowshik Gudimetla

TI__Intellectual 860 points

Thank you Kowshik

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

Hi Ravi,

The MCAL application example you are using is from TI BMS team. From your screenshot, both GPT channel 0 and channel 1 are enabled,.

Did you start channel 1 by calling Gpt_StartTimer(...)? For example Gpt_StartTimer(1, 2000) --> channel 1 and 2ms for tick=1MHz

Ravichandra Sereddy Thipperudra Reddy said:
i am not seeing the callback 'BQ761xNw1GptCbk()'

The BQ761xNw1GptCbk() callback function is defined in gptCallout.c

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Hi Q J,

Yes, i am calling 'Gpt_EnableNotification' and then calling Gpt_StartTimer( channel, time) for both the channels. The MCAL version i am using is 5.40, i also tried in version 6.0.0. Yes we are working on the TI BMS CDD software.

I tried below, and I am seeing the issue in both the cases.

1) Assigning separate counter channels and compare units for the 2 GPT timers.

2) Assigning single counter channel for both the GPT timers and separate compare units for the GPT timers.

I also try enabling the interrupts for all the compare units.

Do you see any issue in the GPT configuration file I shared with you.

Regards,

Ravi

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

Hi Ravi,

BQ761xNw1GptChannel in your configuration uses the RTI compare 2, so the ISR handler should be defined in VIM vector table:

The MCAL driver uses &Gpt_Ch2Isr for RTI compare 2:

Change:

to:

0 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 200246 points

Hi Ravi,

Please share the following files or the whole EB config project

Gpt_PBCfg.c

Gpt_PBCfg.h

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Thank you QJ for the quick response. Attached is the files you asked.for.

I see the GptChannelId '0' and GptCompareUnit '0' is used by OS 'vPortPreemptiveTick' so we cannot use it for our application, Is it possible to use 'BQ761xNw0GptChannel' ( GptChannelId 1, Compare unit 1 ) and 'BQ761xNw1GptChannel' ( GptChannelId 1, Compare unit 2 ) at the same time, if so what is the channel number to pass as argument to Gpt_StartTimer() for each of this.

Fullscreen 4606.sys_vim.c Download

/** @file sys_vim.c 
*   @brief VIM Driver Implementation File
*   @date 11-Dec-2018
*   @version 04.07.01
*
*/

/* 
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
* 
* 
*  Redistribution and use in source and binary forms, with or without 
*  modification, are permitted provided that the following conditions 
*  are met:
*
*    Redistributions of source code must retain the above copyright 
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the 
*    documentation and/or other materials provided with the   
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/



#include "sys_vim.h"
#include "esm.h"
#include "Spi.h"
#include "Gpt_Irq.h"

void Common_Dma_IsrBTC(void);

/* USER CODE BEGIN (0) */

/* Vim Ram Definition */
/** @struct vimRam
*   @brief Vim Ram Definition
*
*   This type is used to access the Vim Ram.
*/
/** @typedef vimRAM_t
*   @brief Vim Ram Type Definition
*
*   This type is used to access the Vim Ram.
*/
typedef volatile struct vimRam
{
    t_isrFuncPTR ISR[VIM_CHANNELS];
} vimRAM_t;

#define vimRAM ((vimRAM_t *)0xFFF82000U)

static const t_isrFuncPTR s_vim_init[128U] =
{
    &phantomInterrupt,
    &esmHighInterrupt,            /* Channel 0 */
    &phantomInterrupt,            /* Channel 1 */
    &vPortPreemptiveTick,         /* Channel 2 */
    &Gpt_Ch1Isr,                  /* Channel 3 */
    &Gpt_Ch2Isr,            /* Channel 4 */
    &phantomInterrupt,            /* Channel 5 */
    &phantomInterrupt,            /* Channel 6 */
    &phantomInterrupt,            /* Channel 7 */
    &phantomInterrupt,            /* Channel 8 */
    &phantomInterrupt,            /* Channel 9 */
    &Icu_HetInt,                  /* Channel 10 */
    &phantomInterrupt,            /* Channel 11 */
    &phantomInterrupt,            /* Channel 12 */
    &phantomInterrupt,            /* Channel 13 */
    &phantomInterrupt,            /* Channel 14 */
    &phantomInterrupt,            /* Channel 15 */
    &phantomInterrupt,            /* Channel 16 */
    &phantomInterrupt,            /* Channel 17 */
    &phantomInterrupt,            /* Channel 18 */
    &phantomInterrupt,            /* Channel 19 */
    &phantomInterrupt,            /* Channel 20 */
    &vPortYeildWithinAPI,         /* Channel 21 */
    &phantomInterrupt,            /* Channel 22 */
    &phantomInterrupt,            /* Channel 23 */
    &phantomInterrupt,            /* Channel 24 */
    &phantomInterrupt,            /* Channel 25 */
    &phantomInterrupt,            /* Channel 26 */
    &phantomInterrupt,            /* Channel 27 */
    &phantomInterrupt,            /* Channel 28 */
    &phantomInterrupt,            /* Channel 29 */
    &phantomInterrupt,            /* Channel 30 */
    &phantomInterrupt,            /* Channel 31 */
    &phantomInterrupt,            /* Channel 32 */
    &phantomInterrupt,            /* Channel 33 */
    &phantomInterrupt,            /* Channel 34 */
    &phantomInterrupt,            /* Channel 35 */
    &phantomInterrupt,            /* Channel 36 */
    &Spi_IrqUnit2TxRxERR,         /* Channel 37 */
    &Spi_IrqUnit2TxRx,         	  /* Channel 38 */
    &phantomInterrupt,            /* Channel 39 */
    &Common_Dma_IsrBTC,           /* Channel 40 */
    &phantomInterrupt,            /* Channel 41 */
    &phantomInterrupt,            /* Channel 42 */
    &phantomInterrupt,            /* Channel 43 */
    &phantomInterrupt,            /* Channel 44 */
    &phantomInterrupt,            /* Channel 45 */
    &phantomInterrupt,            /* Channel 46 */
    &phantomInterrupt,            /* Channel 47 */
    &phantomInterrupt,            /* Channel 48 */
    &Spi_IrqUnit3TxRxERR,         /* Channel 49 */
    &phantomInterrupt,            /* Channel 50 */
    &phantomInterrupt,            /* Channel 51 */
    &phantomInterrupt,            /* Channel 52 */
    &phantomInterrupt,            /* Channel 53 */
    &Spi_IrqUnit3TxRx,            /* Channel 54 */
    &phantomInterrupt,            /* Channel 55 */
    &phantomInterrupt,            /* Channel 56 */
    &phantomInterrupt,            /* Channel 57 */
    &phantomInterrupt,            /* Channel 58 */
    &phantomInterrupt,            /* Channel 59 */
    &phantomInterrupt,            /* Channel 60 */
    &phantomInterrupt,            /* Channel 61 */
    &phantomInterrupt,            /* Channel 62 */
    &phantomInterrupt,            /* Channel 63 */
    &phantomInterrupt,            /* Channel 64 */
    &phantomInterrupt,            /* Channel 65 */
    &phantomInterrupt,            /* Channel 66 */
    &phantomInterrupt,            /* Channel 67 */
    &phantomInterrupt,            /* Channel 68 */
    &phantomInterrupt,            /* Channel 69 */
    &phantomInterrupt,            /* Channel 70 */
    &phantomInterrupt,            /* Channel 71 */
    &phantomInterrupt,            /* Channel 72 */
    &phantomInterrupt,            /* Channel 73 */
    &phantomInterrupt,            /* Channel 74 */
    &phantomInterrupt,            /* Channel 75 */
    &phantomInterrupt,            /* Channel 76 */
    &phantomInterrupt,            /* Channel 77 */
    &phantomInterrupt,            /* Channel 78 */
    &phantomInterrupt,            /* Channel 79 */
    &phantomInterrupt,            /* Channel 80 */
    &phantomInterrupt,            /* Channel 81 */
    &phantomInterrupt,            /* Channel 82 */
    &phantomInterrupt,            /* Channel 83 */
    &phantomInterrupt,            /* Channel 84 */
    &phantomInterrupt,            /* Channel 85 */
    &phantomInterrupt,            /* Channel 86 */
    &phantomInterrupt,            /* Channel 87 */
    &phantomInterrupt,            /* Channel 88 */
    &phantomInterrupt,            /* Channel 89 */
    &phantomInterrupt,            /* Channel 90 */
    &phantomInterrupt,            /* Channel 91 */
    &phantomInterrupt,            /* Channel 92 */
    &phantomInterrupt,            /* Channel 93 */
    &phantomInterrupt,            /* Channel 94 */
    &phantomInterrupt,            /* Channel 95 */
    &phantomInterrupt,            /* Channel 96 */
    &phantomInterrupt,            /* Channel 97 */
    &phantomInterrupt,            /* Channel 98 */
    &phantomInterrupt,            /* Channel 99 */
    &phantomInterrupt,            /* Channel 100 */
    &phantomInterrupt,            /* Channel 101 */
    &phantomInterrupt,            /* Channel 102 */
    &phantomInterrupt,            /* Channel 103 */
    &phantomInterrupt,            /* Channel 104 */
    &phantomInterrupt,            /* Channel 105 */
    &phantomInterrupt,            /* Channel 106 */
    &phantomInterrupt,            /* Channel 107 */
    &phantomInterrupt,            /* Channel 108 */
    &phantomInterrupt,            /* Channel 109 */
    &phantomInterrupt,            /* Channel 110 */
    &phantomInterrupt,            /* Channel 111 */
    &phantomInterrupt,            /* Channel 112 */
    &phantomInterrupt,            /* Channel 113 */
    &phantomInterrupt,            /* Channel 114 */
    &phantomInterrupt,            /* Channel 115 */
    &phantomInterrupt,            /* Channel 116 */
    &phantomInterrupt,            /* Channel 117 */
    &phantomInterrupt,            /* Channel 118 */
    &phantomInterrupt,            /* Channel 119 */
    &phantomInterrupt,            /* Channel 120 */
    &phantomInterrupt,            /* Channel 121 */
    &phantomInterrupt,            /* Channel 122 */
    &phantomInterrupt,            /* Channel 123 */
    &phantomInterrupt,            /* Channel 124 */
    &phantomInterrupt,            /* Channel 125 */
    &phantomInterrupt,            /* Channel 126 */
};
void vimParityErrorHandler(void);

/** @fn void vimInit(void)
*   @brief Initializes VIM module
*
*   This function initializes VIM RAM and registers
*/
/* SourceId : VIM_SourceId_001 */
/* DesignId : VIM_DesignId_001 */
/* Requirements : HL_SR100 */
void vimInit(void)
{
	/* VIM RAM Parity Enable */
	VIM_PARCTL = 0xAU;
	
	/* Initialize VIM table */
    {
        uint32 i;

        for (i = 0U; i < VIM_CHANNELS; i++)
        {
            vimRAM->ISR[i] = s_vim_init[i];
        }
    }
    
    /* Set Fall-Back Address Parity Error Register */
	/*SAFETYMCUSW 439 S MR:11.3 <APPROVED> " Need to store the address of a function in a 32 bit register - Advisory as per MISRA" */
    VIM_FBPARERR = (uint32)&vimParityErrorHandler;

    /* set IRQ/FIQ priorities */
    vimREG->FIRQPR0 = (uint32)((uint32)SYS_FIQ << 0U)
                    | (uint32)((uint32)SYS_FIQ << 1U)
                    | (uint32)((uint32)SYS_IRQ << 2U)
                    | (uint32)((uint32)SYS_IRQ << 3U)
                    | (uint32)((uint32)SYS_IRQ << 4U)
                    | (uint32)((uint32)SYS_IRQ << 5U)
                    | (uint32)((uint32)SYS_IRQ << 6U)
                    | (uint32)((uint32)SYS_IRQ << 7U)
                    | (uint32)((uint32)SYS_IRQ << 8U)
                    | (uint32)((uint32)SYS_IRQ << 9U)
                    | (uint32)((uint32)SYS_IRQ << 10U)
                    | (uint32)((uint32)SYS_IRQ << 11U)
                    | (uint32)((uint32)SYS_IRQ << 12U)
                    | (uint32)((uint32)SYS_IRQ << 13U)
                    | (uint32)((uint32)SYS_IRQ << 14U)
                    | (uint32)((uint32)SYS_IRQ << 15U)
                    | (uint32)((uint32)SYS_IRQ << 16U)
                    | (uint32)((uint32)SYS_IRQ << 17U)
                    | (uint32)((uint32)SYS_IRQ << 18U)
                    | (uint32)((uint32)SYS_IRQ << 19U)
                    | (uint32)((uint32)SYS_IRQ << 20U)
                    | (uint32)((uint32)SYS_IRQ << 21U)
                    | (uint32)((uint32)SYS_IRQ << 22U)
                    | (uint32)((uint32)SYS_IRQ << 23U)
                    | (uint32)((uint32)SYS_IRQ << 24U)
                    | (uint32)((uint32)SYS_IRQ << 25U)
                    | (uint32)((uint32)SYS_IRQ << 26U)
                    | (uint32)((uint32)SYS_IRQ << 27U)
                    | (uint32)((uint32)SYS_IRQ << 28U)
                    | (uint32)((uint32)SYS_IRQ << 29U)
                    | (uint32)((uint32)SYS_IRQ << 30U)
                    | (uint32)((uint32)SYS_IRQ << 31U);

    vimREG->FIRQPR1 = (uint32)((uint32)SYS_IRQ << 0U)
                    | (uint32)((uint32)SYS_IRQ << 1U)
                    | (uint32)((uint32)SYS_IRQ << 2U)
                    | (uint32)((uint32)SYS_IRQ << 3U)
                    | (uint32)((uint32)SYS_IRQ << 4U)
                    | (uint32)((uint32)SYS_IRQ << 5U)
                    | (uint32)((uint32)SYS_IRQ << 6U)
                    | (uint32)((uint32)SYS_IRQ << 7U)
                    | (uint32)((uint32)SYS_IRQ << 8U)
                    | (uint32)((uint32)SYS_IRQ << 9U)
                    | (uint32)((uint32)SYS_IRQ << 10U)
                    | (uint32)((uint32)SYS_IRQ << 11U)
                    | (uint32)((uint32)SYS_IRQ << 12U)
                    | (uint32)((uint32)SYS_IRQ << 13U)
                    | (uint32)((uint32)SYS_IRQ << 14U)
                    | (uint32)((uint32)SYS_IRQ << 15U)
                    | (uint32)((uint32)SYS_IRQ << 16U)
                    | (uint32)((uint32)SYS_IRQ << 17U)
                    | (uint32)((uint32)SYS_IRQ << 18U)
                    | (uint32)((uint32)SYS_IRQ << 19U)
                    | (uint32)((uint32)SYS_IRQ << 20U)
                    | (uint32)((uint32)SYS_IRQ << 21U)
                    | (uint32)((uint32)SYS_IRQ << 22U)
                    | (uint32)((uint32)SYS_IRQ << 23U)
                    | (uint32)((uint32)SYS_IRQ << 24U)
                    | (uint32)((uint32)SYS_IRQ << 25U)
                    | (uint32)((uint32)SYS_IRQ << 26U)
                    | (uint32)((uint32)SYS_IRQ << 27U)
                    | (uint32)((uint32)SYS_IRQ << 28U)
                    | (uint32)((uint32)SYS_IRQ << 29U)
                    | (uint32)((uint32)SYS_IRQ << 30U)
                    | (uint32)((uint32)SYS_IRQ << 31U);


    vimREG->FIRQPR2 = (uint32)((uint32)SYS_IRQ << 0U)
                    | (uint32)((uint32)SYS_IRQ << 1U)
                    | (uint32)((uint32)SYS_IRQ << 2U)
                    | (uint32)((uint32)SYS_IRQ << 3U)
                    | (uint32)((uint32)SYS_IRQ << 4U)
                    | (uint32)((uint32)SYS_IRQ << 5U)
                    | (uint32)((uint32)SYS_IRQ << 6U)
                    | (uint32)((uint32)SYS_IRQ << 7U)
                    | (uint32)((uint32)SYS_IRQ << 8U)
                    | (uint32)((uint32)SYS_IRQ << 9U)
                    | (uint32)((uint32)SYS_IRQ << 10U)
                    | (uint32)((uint32)SYS_IRQ << 11U)
                    | (uint32)((uint32)SYS_IRQ << 12U)
                    | (uint32)((uint32)SYS_IRQ << 13U)
                    | (uint32)((uint32)SYS_IRQ << 14U)
                    | (uint32)((uint32)SYS_IRQ << 15U)
                    | (uint32)((uint32)SYS_IRQ << 16U)
                    | (uint32)((uint32)SYS_IRQ << 17U)
                    | (uint32)((uint32)SYS_IRQ << 18U)
                    | (uint32)((uint32)SYS_IRQ << 19U)
                    | (uint32)((uint32)SYS_IRQ << 20U)
                    | (uint32)((uint32)SYS_IRQ << 21U)
                    | (uint32)((uint32)SYS_IRQ << 22U)
                    | (uint32)((uint32)SYS_IRQ << 23U)
                    | (uint32)((uint32)SYS_IRQ << 24U)
                    | (uint32)((uint32)SYS_IRQ << 25U)
                    | (uint32)((uint32)SYS_IRQ << 26U)
                    | (uint32)((uint32)SYS_IRQ << 27U)
                    | (uint32)((uint32)SYS_IRQ << 28U)
                    | (uint32)((uint32)SYS_IRQ << 29U)
                    | (uint32)((uint32)SYS_IRQ << 30U)
                    | (uint32)((uint32)SYS_IRQ << 31U);

    vimREG->FIRQPR3 = (uint32)((uint32)SYS_IRQ << 0U)
                    | (uint32)((uint32)SYS_IRQ << 1U)
                    | (uint32)((uint32)SYS_IRQ << 2U)
                    | (uint32)((uint32)SYS_IRQ << 3U)
                    | (uint32)((uint32)SYS_IRQ << 4U)
                    | (uint32)((uint32)SYS_IRQ << 5U)
                    | (uint32)((uint32)SYS_IRQ << 6U)
                    | (uint32)((uint32)SYS_IRQ << 7U)
                    | (uint32)((uint32)SYS_IRQ << 8U)
                    | (uint32)((uint32)SYS_IRQ << 9U)
                    | (uint32)((uint32)SYS_IRQ << 10U)
                    | (uint32)((uint32)SYS_IRQ << 11U)
                    | (uint32)((uint32)SYS_IRQ << 12U)
                    | (uint32)((uint32)SYS_IRQ << 13U)
                    | (uint32)((uint32)SYS_IRQ << 14U)
                    | (uint32)((uint32)SYS_IRQ << 15U)
                    | (uint32)((uint32)SYS_IRQ << 16U)
                    | (uint32)((uint32)SYS_IRQ << 17U)
                    | (uint32)((uint32)SYS_IRQ << 18U)
                    | (uint32)((uint32)SYS_IRQ << 19U)
                    | (uint32)((uint32)SYS_IRQ << 20U)
                    | (uint32)((uint32)SYS_IRQ << 21U)
                    | (uint32)((uint32)SYS_IRQ << 22U)
                    | (uint32)((uint32)SYS_IRQ << 23U)
                    | (uint32)((uint32)SYS_IRQ << 24U)
                    | (uint32)((uint32)SYS_IRQ << 25U)
                    | (uint32)((uint32)SYS_IRQ << 26U)
                    | (uint32)((uint32)SYS_IRQ << 27U)
                    | (uint32)((uint32)SYS_IRQ << 28U)
                    | (uint32)((uint32)SYS_IRQ << 29U)
                    | (uint32)((uint32)SYS_IRQ << 30U)
                    | (uint32)((uint32)SYS_IRQ << 31U);

                    
    /* enable interrupts */
    vimREG->REQMASKSET0 = (uint32)((uint32)1U << 0U)
                        | (uint32)((uint32)1U << 1U)
                        | (uint32)((uint32)1U << 2U)
                        | (uint32)((uint32)1U << 3U)
                        | (uint32)((uint32)1U << 4U)
                        | (uint32)((uint32)1U << 5U)
                        | (uint32)((uint32)0U << 6U)
                        | (uint32)((uint32)0U << 7U)
                        | (uint32)((uint32)0U << 8U)
                        | (uint32)((uint32)0U << 9U)
                        | (uint32)((uint32)1U << 10U)
                        | (uint32)((uint32)0U << 11U)
                        | (uint32)((uint32)0U << 12U)
                        | (uint32)((uint32)0U << 13U)
                        | (uint32)((uint32)0U << 14U)
                        | (uint32)((uint32)0U << 15U)
                        | (uint32)((uint32)0U << 16U)
                        | (uint32)((uint32)0U << 17U)
                        | (uint32)((uint32)0U << 18U)
                        | (uint32)((uint32)0U << 19U)
                        | (uint32)((uint32)0U << 20U)
                        | (uint32)((uint32)1U << 21U)
                        | (uint32)((uint32)0U << 22U)
                        | (uint32)((uint32)0U << 23U)
                        | (uint32)((uint32)0U << 24U)
                        | (uint32)((uint32)0U << 25U)
                        | (uint32)((uint32)0U << 26U)
                        | (uint32)((uint32)0U << 27U)
                        | (uint32)((uint32)0U << 28U)
                        | (uint32)((uint32)0U << 29U)
                        | (uint32)((uint32)0U << 30U)
                        | (uint32)((uint32)0U << 31U);

    vimREG->REQMASKSET1 = (uint32)((uint32)0U << 0U)
                        | (uint32)((uint32)0U << 1U)
                        | (uint32)((uint32)0U << 2U)
                        | (uint32)((uint32)0U << 3U)
                        | (uint32)((uint32)0U << 4U)
                        | (uint32)((uint32)1U << 5U)
                        | (uint32)((uint32)1U << 6U)
                        | (uint32)((uint32)0U << 7U)
                        | (uint32)((uint32)1U << 8U)
                        | (uint32)((uint32)0U << 9U)
                        | (uint32)((uint32)0U << 10U)
                        | (uint32)((uint32)0U << 11U)
                        | (uint32)((uint32)0U << 12U)
                        | (uint32)((uint32)0U << 13U)
                        | (uint32)((uint32)0U << 14U)
                        | (uint32)((uint32)0U << 15U)
                        | (uint32)((uint32)0U << 16U)
                        | (uint32)((uint32)1U << 17U)
                        | (uint32)((uint32)0U << 18U)
                        | (uint32)((uint32)0U << 19U)
                        | (uint32)((uint32)0U << 20U)
                        | (uint32)((uint32)0U << 21U)
                        | (uint32)((uint32)1U << 22U)
                        | (uint32)((uint32)0U << 23U)
                        | (uint32)((uint32)0U << 24U)
                        | (uint32)((uint32)0U << 25U)
                        | (uint32)((uint32)0U << 26U)
                        | (uint32)((uint32)0U << 27U)
                        | (uint32)((uint32)0U << 28U)
                        | (uint32)((uint32)0U << 29U)
                        | (uint32)((uint32)0U << 30U)
                        | (uint32)((uint32)0U << 31U);

    vimREG->REQMASKSET2 = (uint32)((uint32)0U << 0U)
                        | (uint32)((uint32)0U << 1U)
                        | (uint32)((uint32)0U << 2U)
                        | (uint32)((uint32)0U << 3U)
                        | (uint32)((uint32)0U << 4U)
                        | (uint32)((uint32)0U << 5U)
                        | (uint32)((uint32)0U << 6U)
                        | (uint32)((uint32)0U << 7U)
                        | (uint32)((uint32)0U << 8U)
                        | (uint32)((uint32)0U << 9U)
                        | (uint32)((uint32)0U << 10U)
                        | (uint32)((uint32)0U << 11U)
                        | (uint32)((uint32)0U << 12U)
                        | (uint32)((uint32)0U << 13U)
                        | (uint32)((uint32)0U << 14U)
                        | (uint32)((uint32)0U << 15U)
                        | (uint32)((uint32)0U << 16U)
                        | (uint32)((uint32)0U << 17U)
                        | (uint32)((uint32)0U << 18U)
                        | (uint32)((uint32)0U << 19U)
                        | (uint32)((uint32)0U << 20U)
                        | (uint32)((uint32)0U << 21U)
                        | (uint32)((uint32)0U << 22U)
                        | (uint32)((uint32)0U << 23U)
                        | (uint32)((uint32)0U << 24U)
                        | (uint32)((uint32)0U << 25U)
                        | (uint32)((uint32)0U << 26U)
                        | (uint32)((uint32)0U << 27U)
                        | (uint32)((uint32)0U << 28U)
                        | (uint32)((uint32)0U << 29U)
                        | (uint32)((uint32)0U << 30U)
                        | (uint32)((uint32)0U << 31U);
                        
    vimREG->REQMASKSET3 = (uint32)((uint32)0U << 0U)
                        | (uint32)((uint32)0U << 1U)
                        | (uint32)((uint32)0U << 2U)
                        | (uint32)((uint32)0U << 3U)
                        | (uint32)((uint32)0U << 4U)
                        | (uint32)((uint32)0U << 5U)
                        | (uint32)((uint32)0U << 6U)
                        | (uint32)((uint32)0U << 7U)
                        | (uint32)((uint32)0U << 8U)
                        | (uint32)((uint32)0U << 9U)
                        | (uint32)((uint32)0U << 10U)
                        | (uint32)((uint32)0U << 11U)
                        | (uint32)((uint32)0U << 12U)
                        | (uint32)((uint32)0U << 13U)
                        | (uint32)((uint32)0U << 14U)
                        | (uint32)((uint32)0U << 15U)
                        | (uint32)((uint32)0U << 16U)
                        | (uint32)((uint32)0U << 17U)
                        | (uint32)((uint32)0U << 18U)
                        | (uint32)((uint32)0U << 19U)
                        | (uint32)((uint32)0U << 20U)
                        | (uint32)((uint32)0U << 21U)
                        | (uint32)((uint32)0U << 22U)
                        | (uint32)((uint32)0U << 23U)
                        | (uint32)((uint32)0U << 24U)
                        | (uint32)((uint32)0U << 25U)
                        | (uint32)((uint32)0U << 26U)
                        | (uint32)((uint32)0U << 27U)
                        | (uint32)((uint32)0U << 28U)
                        | (uint32)((uint32)0U << 29U)
                        | (uint32)((uint32)0U << 30U)
                        | (uint32)((uint32)0U << 31U);    

    /* Set Capture event sources */
	vimREG->CAPEVT = ((uint32)((uint32)0U << 0U)
	                 |(uint32)((uint32)0U << 16U));
}

/** @fn void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
*   @brief Map selected interrupt request to the selected channel
*
*    @param[in] request: Interrupt request number 2..127
*    @param[in] channel: VIM Channel number 2..127
*    @param[in] handler: Address of the interrupt handler
*
*   This function will map selected interrupt request to the selected channel.
*
*/
/* SourceId : VIM_SourceId_002 */
/* DesignId : VIM_DesignId_002 */
/* Requirements : HL_SR101 */
void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
{
    uint32 i,j;
    i = channel >> 2U;              /* Find the register to configure */
    j = channel - (i << 2U);        /* Find the offset of the type    */
    j = 3U - j;                     /* reverse the byte order         */
    j = j << 3U;                    /* find the bit location          */

    /*Mapping the required interrupt request to the required channel*/
    vimREG->CHANCTRL[i] &= ~(uint32)((uint32)0xFFU << j);
    vimREG->CHANCTRL[i] |= (request << j);

    /*Updating VIMRAM*/
    vimRAM->ISR[channel + 1U] = handler;
}

/** @fn void vimEnableInterrupt(uint32 channel, boolean inttype)
*   @brief Enable interrupt for the the selected channel
*
*    @param[in] channel: VIM Channel number 2..127
*    @param[in] inttype: Interrupt type
*                        - SYS_IRQ: Selected channel will be enabled as IRQ
*                        - SYS_FIQ: Selected channel will be enabled as FIQ
*
*   This function will enable interrupt for the selected channel.
*
*/
/* SourceId : VIM_SourceId_003 */
/* DesignId : VIM_DesignId_003 */
/* Requirements : HL_SR102 */
void vimEnableInterrupt(uint32 channel, systemInterrupt_t inttype)
{
	if (channel >= 96U)
    {
        if(inttype == SYS_IRQ)
        {
            vimREG->FIRQPR3 &= ~(uint32)((uint32)1U << (channel-96U));
        }
        else
        {
            vimREG->FIRQPR3 |= ((uint32)1U << (channel-96U));
        }
        vimREG->REQMASKSET3 = (uint32)1U << (channel-96U);
    }
    else if (channel >= 64U)
    {
        if(inttype == SYS_IRQ)
        {
            vimREG->FIRQPR2 &= ~(uint32)((uint32)1U << (channel-64U));
        }
        else
        {
            vimREG->FIRQPR2 |= ((uint32)1U << (channel-64U));
        }
        vimREG->REQMASKSET2 = (uint32)1U << (channel-64U);
    }
    else if (channel >= 32U)
    {
        if(inttype == SYS_IRQ)
        {
            vimREG->FIRQPR1 &= ~(uint32)((uint32)1U << (channel-32U));
        }
        else
        {
            vimREG->FIRQPR1 |= ((uint32)1U << (channel-32U));
        }
        vimREG->REQMASKSET1 = (uint32)1U << (channel-32U);
    }
    else if (channel >= 2U)
    {
        if(inttype == SYS_IRQ)
        {
            vimREG->FIRQPR0 &= ~(uint32)((uint32)1U << channel);
        }
        else
        {
            vimREG->FIRQPR0 |= ((uint32)1U << channel);
        }
        vimREG->REQMASKSET0 = (uint32)1U << channel;
    }
    else
    {
		/* Empty */
    }
}

/** @fn void vimDisableInterrupt(uint32 channel)
*   @brief Disable interrupt for the the selected channel
*
*    @param[in] channel: VIM Channel number 2..127
*
*   This function will disable interrupt for the selected channel.
*
*/
/* SourceId : VIM_SourceId_004 */
/* DesignId : VIM_DesignId_004 */
/* Requirements : HL_SR103 */
void vimDisableInterrupt(uint32 channel)
{
    if (channel >= 96U)
    {
        vimREG->REQMASKCLR3 = (uint32)1U << (channel-96U);
    }
    else if (channel >= 64U)
    {
        vimREG->REQMASKCLR2 = (uint32)1U << (channel-64U);
    }
    else if (channel >=32U)
    {
        vimREG->REQMASKCLR1 = (uint32)1U << (channel-32U);
    }
    else if (channel >= 2U)
    {
        vimREG->REQMASKCLR0 = (uint32)1U << channel;
    }
    else
    {
		/* Empty */
    }
}

/* USER CODE BEGIN (1) */
/* USER CODE END */

/** @fn void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
*   @brief Get the initial or current values of the configuration registers
*
*    @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
*    @param[in] type:     whether initial or current value of the configuration registers need to be stored
*                        - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
*                        - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
*
*   This function will copy the initial or current value (depending on the parameter 'type') of the configuration 
*   registers to the struct pointed by config_reg
*
*/
/* SourceId : VIM_SourceId_005 */
/* DesignId : VIM_DesignId_005 */
/* Requirements : HL_SR104 */
void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
{  
    if (type == InitialValue)
    {
        config_reg->CONFIG_FIRQPR0 = VIM_FIRQPR0_CONFIGVALUE;
        config_reg->CONFIG_FIRQPR1 = VIM_FIRQPR1_CONFIGVALUE;
        config_reg->CONFIG_FIRQPR2 = VIM_FIRQPR2_CONFIGVALUE;
        config_reg->CONFIG_FIRQPR3 = VIM_FIRQPR3_CONFIGVALUE;
        config_reg->CONFIG_REQMASKSET0 = VIM_REQMASKSET0_CONFIGVALUE;
        config_reg->CONFIG_REQMASKSET1 = VIM_REQMASKSET1_CONFIGVALUE;
        config_reg->CONFIG_REQMASKSET2 = VIM_REQMASKSET2_CONFIGVALUE;
        config_reg->CONFIG_REQMASKSET3 = VIM_REQMASKSET3_CONFIGVALUE;
        config_reg->CONFIG_WAKEMASKSET0 = VIM_WAKEMASKSET0_CONFIGVALUE;
        config_reg->CONFIG_WAKEMASKSET1 = VIM_WAKEMASKSET1_CONFIGVALUE;
        config_reg->CONFIG_WAKEMASKSET2 = VIM_WAKEMASKSET2_CONFIGVALUE;
        config_reg->CONFIG_WAKEMASKSET3 = VIM_WAKEMASKSET3_CONFIGVALUE;
        config_reg->CONFIG_CAPEVT = VIM_CAPEVT_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[0U] = VIM_CHANCTRL0_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[1U] = VIM_CHANCTRL1_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[2U] = VIM_CHANCTRL2_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[3U] = VIM_CHANCTRL3_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[4U] = VIM_CHANCTRL4_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[5U] = VIM_CHANCTRL5_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[6U] = VIM_CHANCTRL6_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[7U] = VIM_CHANCTRL7_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[8U] = VIM_CHANCTRL8_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[9U] = VIM_CHANCTRL9_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[10U] = VIM_CHANCTRL10_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[11U] = VIM_CHANCTRL11_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[12U] = VIM_CHANCTRL12_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[13U] = VIM_CHANCTRL13_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[14U] = VIM_CHANCTRL14_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[15U] = VIM_CHANCTRL15_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[16U] = VIM_CHANCTRL16_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[17U] = VIM_CHANCTRL17_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[18U] = VIM_CHANCTRL18_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[19U] = VIM_CHANCTRL19_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[20U] = VIM_CHANCTRL20_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[21U] = VIM_CHANCTRL21_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[22U] = VIM_CHANCTRL22_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[23U] = VIM_CHANCTRL23_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[24U] = VIM_CHANCTRL24_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[25U] = VIM_CHANCTRL25_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[26U] = VIM_CHANCTRL26_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[27U] = VIM_CHANCTRL27_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[28U] = VIM_CHANCTRL28_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[29U] = VIM_CHANCTRL29_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[30U] = VIM_CHANCTRL30_CONFIGVALUE;
		config_reg->CONFIG_CHANCTRL[31U] = VIM_CHANCTRL31_CONFIGVALUE;
    }
    else
    {
	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
        config_reg->CONFIG_FIRQPR0 = vimREG->FIRQPR0;
        config_reg->CONFIG_FIRQPR1 = vimREG->FIRQPR1;
        config_reg->CONFIG_FIRQPR2 = vimREG->FIRQPR2;
        config_reg->CONFIG_FIRQPR3 = vimREG->FIRQPR3;
        config_reg->CONFIG_REQMASKSET0 = vimREG->REQMASKSET0;
        config_reg->CONFIG_REQMASKSET1 = vimREG->REQMASKSET1;
        config_reg->CONFIG_REQMASKSET2 = vimREG->REQMASKSET2;
        config_reg->CONFIG_REQMASKSET3 = vimREG->REQMASKSET3;
        config_reg->CONFIG_WAKEMASKSET0 = vimREG->WAKEMASKSET0;
        config_reg->CONFIG_WAKEMASKSET1 = vimREG->WAKEMASKSET1;
        config_reg->CONFIG_WAKEMASKSET2 = vimREG->WAKEMASKSET2;
        config_reg->CONFIG_WAKEMASKSET3 = vimREG->WAKEMASKSET3;
        config_reg->CONFIG_CAPEVT = vimREG->CAPEVT;
		config_reg->CONFIG_CHANCTRL[0U] = vimREG->CHANCTRL[0U];
		config_reg->CONFIG_CHANCTRL[1U] = vimREG->CHANCTRL[1U];
		config_reg->CONFIG_CHANCTRL[2U] = vimREG->CHANCTRL[2U];
		config_reg->CONFIG_CHANCTRL[3U] = vimREG->CHANCTRL[3U];
		config_reg->CONFIG_CHANCTRL[4U] = vimREG->CHANCTRL[4U];
		config_reg->CONFIG_CHANCTRL[5U] = vimREG->CHANCTRL[5U];
		config_reg->CONFIG_CHANCTRL[6U] = vimREG->CHANCTRL[6U];
		config_reg->CONFIG_CHANCTRL[7U] = vimREG->CHANCTRL[7U];
		config_reg->CONFIG_CHANCTRL[8U] = vimREG->CHANCTRL[8U];
		config_reg->CONFIG_CHANCTRL[9U] = vimREG->CHANCTRL[9U];
		config_reg->CONFIG_CHANCTRL[10U] = vimREG->CHANCTRL[10U];
		config_reg->CONFIG_CHANCTRL[11U] = vimREG->CHANCTRL[11U];
		config_reg->CONFIG_CHANCTRL[12U] = vimREG->CHANCTRL[12U];
		config_reg->CONFIG_CHANCTRL[13U] = vimREG->CHANCTRL[13U];
		config_reg->CONFIG_CHANCTRL[14U] = vimREG->CHANCTRL[14U];
		config_reg->CONFIG_CHANCTRL[15U] = vimREG->CHANCTRL[15U];
		config_reg->CONFIG_CHANCTRL[16U] = vimREG->CHANCTRL[16U];
		config_reg->CONFIG_CHANCTRL[17U] = vimREG->CHANCTRL[17U];
		config_reg->CONFIG_CHANCTRL[18U] = vimREG->CHANCTRL[18U];
		config_reg->CONFIG_CHANCTRL[19U] = vimREG->CHANCTRL[19U];
		config_reg->CONFIG_CHANCTRL[20U] = vimREG->CHANCTRL[20U];
		config_reg->CONFIG_CHANCTRL[21U] = vimREG->CHANCTRL[21U];
		config_reg->CONFIG_CHANCTRL[22U] = vimREG->CHANCTRL[22U];
		config_reg->CONFIG_CHANCTRL[23U] = vimREG->CHANCTRL[23U];
		config_reg->CONFIG_CHANCTRL[24U] = vimREG->CHANCTRL[24U];
		config_reg->CONFIG_CHANCTRL[25U] = vimREG->CHANCTRL[25U];
		config_reg->CONFIG_CHANCTRL[26U] = vimREG->CHANCTRL[26U];
		config_reg->CONFIG_CHANCTRL[27U] = vimREG->CHANCTRL[27U];
		config_reg->CONFIG_CHANCTRL[28U] = vimREG->CHANCTRL[28U];
		config_reg->CONFIG_CHANCTRL[29U] = vimREG->CHANCTRL[29U];
		config_reg->CONFIG_CHANCTRL[30U] = vimREG->CHANCTRL[30U];
		config_reg->CONFIG_CHANCTRL[31U] = vimREG->CHANCTRL[31U];
    }
}


#pragma CODE_STATE(vimParityErrorHandler, 32)
#pragma INTERRUPT(vimParityErrorHandler, IRQ)
#pragma WEAK(vimParityErrorHandler)

/* SourceId : VIM_SourceId_006 */
/* DesignId : VIM_DesignId_006 */
/* Requirements : HL_SR105 */
void vimParityErrorHandler(void)
{
    uint32 vec;
    
    /* Identify the corrupted address */
    uint32 error_addr = VIM_ADDERR;

    /* Identify the channel number */
    uint32 error_channel = ((error_addr & 0x1FFU) >> 2U);

    /* Correct the corrupted location */
    vimRAM->ISR[error_channel] = s_vim_init[error_channel];

    /* Clear Parity Error Flag */
    VIM_PARFLG = 1U;

    /* Disable and enable the highest priority pending channel */
    if (vimREG->FIQINDEX != 0U)
    {
        vec = vimREG->FIQINDEX - 1U;
    }
    else 
    {
	   /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Read 32 bit volatile register" */
        vec = vimREG->IRQINDEX - 1U;
    }
    if(vec == 0U)
    {
        vimREG->INTREQ0 = 1U;
	    vec = esmREG->IOFFHR - 1U;
		
        if (vec < 32U)
        {
            esmREG->SR1[0U] = (uint32)1U << vec;
            esmGroup1Notification(vec);
        }
        else if (vec < 64U)
        {
            esmREG->SR1[1U] = (uint32)1U << (vec-32U);
            esmGroup2Notification(vec-32U);
        }
        else if (vec < 96U)
        {
            esmREG->SR4[0U] = (uint32)1U << (vec-64U);
            esmGroup1Notification(vec-32U);
        }
        else
        {
            esmREG->SR4[1U] = (uint32)1U << (vec-96U);
            esmGroup2Notification(vec-64U);
        }
    }
    else if (vec < 32U)
    {
        vimREG->REQMASKCLR0 = (uint32)1U << vec;
        vimREG->REQMASKSET0 = (uint32)1U << vec;
    }
    else if (vec < 64U)
    {
        vimREG->REQMASKCLR1 = (uint32)1U << (vec-32U);
        vimREG->REQMASKSET1 = (uint32)1U << (vec-32U);
    }
    else if(vec < 96U)
    {
        vimREG->REQMASKCLR2 = (uint32)1U << (vec-64U);
        vimREG->REQMASKSET2 = (uint32)1U << (vec-64U);
    }
	else
	{
	    vimREG->REQMASKCLR3 = (uint32)1U << (vec-96U);
        vimREG->REQMASKSET3 = (uint32)1U << (vec-96U);
	}
}

Fullscreen Gpt_PBcfg.c Download

/**********************************************************************************************************************
 *  COPYRIGHT
 *  -------------------------------------------------------------------------------------------------------------------
 *  \verbatim
 *
 *                 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
 *
 *                 Property of Texas Instruments, Unauthorized reproduction and/or distribution
 *                 is strictly prohibited.  This product  is  protected  under  copyright  law
 *                 and  trade  secret law as an  unpublished work.
 *                 (C) Copyright Texas Instruments.  All rights reserved.
 *
 *  \endverbatim
 *  -------------------------------------------------------------------------------------------------------------------
 *  FILE DESCRIPTION
 *  -------------------------------------------------------------------------------------------------------------------
 *         File:  Gpt_PBCfg.c
 *      Project:  Tms570_AutosarGptDriver
 *       Module:  GptDriver
 *    Generator:  EB Tresos
 *
 *  Description:  This component provides services for initialization and control of the microcontroller internal
 *                GPT unit (General Purpose Timer).
 *  
 *********************************************************************************************************************/

/*********************************************************************************************************************
/ *---------------------------------------------------------------------------------------------------------------------
 * Author:  Vishwanath Reddy
 *---------------------------------------------------------------------------------------------------------------------
 * Revision History
 *---------------------------------------------------------------------------------------------------------------------
 * Version        Date         Author               Change ID        Description
 *---------------------------------------------------------------------------------------------------------------------
 * 02.21.00       30Sep14      Vishwanath Reddy     SDOCM00113130    Initial Version
 * 02.21.01       11Mar16      Enrique Lizarraga    SDOCM00121245    Correct GptChannelId type from Enum to Int
 * 02.30.00       01Dec2016    Sudhakar Singh           None         Update version info
 * 05.30.00       15Mar2017    Sudhakar Singh       SDOCM00122834    Version supports TMS570LSxx Family of Devices.
 * 05.40.00       25Jul2018    Vishwanath Reddy     HERCULES_SW-6043 GptChannelId configuration in XDM changed to
 *                                                                   support 0 and 1 instead of 1 and 2.
 *                                                  HERCULES_SW-6071 Support for configuring required Compare unit.
 *                                                                   Also all global registers are now used as Read-  
 *                                                                   Modify-Write so as to not disturb the existing
 *                                                                   configuration.
 *********************************************************************************************************************/
/*********************************************************************************************************************
    Project: MCAL_EB_Prj
    Date   : 2022-11-05 23:22:35 
    
    This file is generated by EB Tresos 
    Do not modify this file, otherwise the software may behave in unexpected way.
    
**********************************************************************************************************************/
#include "Std_Types.h"
#include "Gpt.h"
#include "Gpt_Cfg.h"

#define GPT_CFG_C_MAJOR_VERSION               (5U)
#define GPT_CFG_C_MINOR_VERSION               (40U)
#define GPT_CFG_C_PATCH_VERSION               (0U)

/* ---- Perform version checking  ----------------------------------------- */
#if (   (GPT_SW_MAJOR_VERSION != GPT_CFG_C_MAJOR_VERSION) \
     || (GPT_SW_MINOR_VERSION != GPT_CFG_C_MINOR_VERSION))
  #error "Version numbers of Gpt_PBcfg.c and Gpt.h are inconsistent!"
#endif

#if (   (GPT_CFG_MAJOR_VERSION != GPT_CFG_C_MAJOR_VERSION) \
     || (GPT_CFG_MINOR_VERSION != GPT_CFG_C_MINOR_VERSION))
  #error "Version numbers of Gpt_PBcfg.c and Gpt_Cfg.h are inconsistent!"
#endif

#define GPT_START_SEC_CONST_PBCFG_ROOT
/*SAFETYMCUSW 338 S MR:19.1 <APPROVED> "Reason - This is the format to use for specifying memorysections."*/
#include "MemMap.h"



/* Gpt Channel Configuration parameters */

static CONST(Gpt_ChannelConfigType, GPT_PBCFG) Gpt_ChannelConfig0[3] = 
{
  
  {
    0, /*RTI counter block used*/
	0, /* RTI Compare Unit used*/
	FALSE, /* Is Channel used */	
    GPT_CH_MODE_CONTINUOUS,/* Gpt Channel Mode */
    0U,/* Channel Frequency in MHz*/ 
    0xffffffffU,/*Max Channel Tick Value*/
    FALSE,/*Wakeup Enable Flag*/
    NULL_PTR,/*Notification Call Back function*/
    80U, /* Gpt Clock derived from Mcu in MHz. This parameter is not used in GPT module.*/ 
    0U
  },
  {
    1, /*RTI counter block used*/
	1, /* RTI Compare Unit used*/
	TRUE, /* Is Channel used */	
    GPT_CH_MODE_ONESHOT,/* Gpt Channel Mode */
    6U,/* Channel Frequency in MHz*/ 
    0xffffffffU,/*Max Channel Tick Value*/
    FALSE,/*Wakeup Enable Flag*/
    BQ761xNw0GptCbk,/*Notification Call Back function*/
    80U, /* Gpt Clock derived from Mcu in MHz. This parameter is not used in GPT module.*/ 
    0U
  },
  {
    1, /*RTI counter block used*/
	2, /* RTI Compare Unit used*/
	TRUE, /* Is Channel used */	
    GPT_CH_MODE_ONESHOT,/* Gpt Channel Mode */
    6U,/* Channel Frequency in MHz*/ 
    0xffffffffU,/*Max Channel Tick Value*/
    FALSE,/*Wakeup Enable Flag*/
    BQ761xNw1GptCbk,/*Notification Call Back function*/
    80U, /* Gpt Clock derived from Mcu in MHz. This parameter is not used in GPT module.*/ 
    0U
  }
};


/*<GPT_CONFIGURATION>*/




CONST(Gpt_ConfigType, GPT_PBCFG) GptChannelConfigSet_0 =
{
  Gpt_ChannelConfig0,/*Pointer to Channel Configuration*/
  3/*Number of Channels*/
};

/*</GPT_CONFIGURATION>*/

#define GPT_STOP_SEC_CONST_PBCFG_ROOT
/*SAFETYMCUSW 338 S MR:19.1 <APPROVED> "Reason - This is the format to use for specifying memorysections."*/
#include "MemMap.h"

/*----- End of File --------------------------------------------------------*/

Gpt_Cfg.hhttps://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/7317.Gpt.xdm

Thanks,

Ravi

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

Hi Ravi,

I am not able to open your Gpt.xdm since the project configuration is required to open module config GUI.

From the text editor, I know that both RTI counters (counter 0, and counter 1) are used, and three compare registers are used:

Compare register 0 --> use counter 0 --> GptOsTick

Compare register 1 --> use counter 1 --> BQ761xNw0GptChannel

Compare register 2 --> use counter 2 --> BQ761xNw1GptChannel

Ravichandra Sereddy Thipperudra Reddy said:
Is it possible to use 'BQ761xNw0GptChannel' ( GptChannelId 1, Compare unit 1 ) and 'BQ761xNw1GptChannel' ( GptChannelId 1, Compare unit 2 ) at the same time,

Yes, you can use them at a time. The RTI supports upto 4 compare registers.

Ravichandra Sereddy Thipperudra Reddy said:
if so what is the channel number to pass as argument to Gpt_StartTimer() for each of this.

The channel ID in Gpt_StartTimer(ChannelID, timeValue) is number of counter: counre0 or counter 1. In your case, counter 1 is used for BQ761xNw0GptChannel and BQ761xNw1GptChannel.

The timeValue (2nd parameter in Gpt_StartTimer()) is the compare value programmed to compare register (RTICOMP1/2) and update compare register (RTIUDCP1/2).

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Hi Q J,

Thank you for the kind response. Our application needs to use 'BQ761xNw0GptChannel' and 'BQ761xNw1GptChannel' in parallel (not one at a time) at the same time, so its not possible to do with the same counter value '1' for both the channels. Is my understanding correct.

Also, I see the generated channel numbers are incorrect

Regards,

Ravi

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

Hi Ravi,

Ravichandra Sereddy Thipperudra Reddy said:
its not possible to do with the same counter value '1' for both the channels

They can use the same counter at the same time.

This is the RTI application ID or the number of compare unit. BQ761xNw0GptChannel uses compare 1, and BQ761xNw1GptChannel uses compare 2. The number here (0, 1, 2) doesn't stand for the number of RTI counter (0 or 1).

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Thank you QJ, I mean we can't call Gpt_StartTimer() for both BQ761xNw0GptChannel and BQ761xNw1GptChannel as below, since both use the same channel number . We tried it and its not working for us ( In the below case only BQ761xNw1GptChannel is working and receiving the call back .'BQ761xNw1GptCbk()' )

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

After Com_Gpt_StartTime(COM_GPT_CHANNEL, ..) is called, are the RTI Compare1 registers programmed: RTICOMP1 and RTIUDCP1?

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Hi Q J,

Below is the screenshot of the register contents, when Com_Gpt_StartTime(COM_GPT_CHANNEL, ..) is called

Also I see the 'BQ761xNw1GptCbk()'' is triggered from 'Gpt_Ch1Isr' instead I think it should be triggered from 'GPT_Ch2Isr'

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

COM_GPT_CHANNEL = BQ761xNw0GptChannel --> using compare unit 1 and counter 1 --> not working

BQ761xNw1GptChannel --> using compare unit 2 and counter 1 ---> working

The RTIUDCP1 is not programmed. This means it can generate one interrupt only. It should be fine for ONE_SHOT mode.

The RTIUDCP2 and RTICMP2 are not programmed, This BQ761xNw1GptChannel won't work.

0 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 200246 points

I think I found the root cause. There is a SW bug in Gpt_SetRegStartTimer() in Gpt.c file.

For one-shot mode, only GPT_RTI1_COMP0 is programmed if counter 0 is used, and only GPT_RTI1_COMP1 is programmed if counter 1 is used.

In your case, counter 1 is used for compare 1 and compare 2, only GPT_RTI_COMP1 is programmed, and GPT_RTI_COMP2 is programmed, so BQ761xNw1GptChannel does not work.

Maybe this is the MCAL limitation.

Can you modify the driver and try?

change to:

Gpt_ChannelNotifyFunctions[Gpt_Channel] = Gpt_Config_pt->ChannelConfig_pt[channel].Notification_pt;
if(ChannelMode_t == GPT_CH_MODE_ONESHOT)
{
GPT_RTI1_COMP1 = value;
switch(Gpt_Config_pt->ChannelConfig_pt[channel].CompareUnit)
{
case RTI1_COMPARE0:

GPT_RTI1_COMP0 = value;
GPT_RTI1_UDCP0 = 0U;
break;

case RTI1_COMPARE1:

GPT_RTI1_COMP1 = value;

GPT_RTI1_UDCP1 = 0U;
break;

case RTI1_COMPARE2:

GPT_RTI1_COMP2 = value;
GPT_RTI1_UDCP2 = 0U;
break;

case RTI1_COMPARE3:

GPT_RTI1_COMP3 = value;
GPT_RTI1_UDCP3 = 0U;
break;

default:
break;

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Thank you Q J for the quick response.

In 'Gpt_SetRegStartTimer(), I see for all the 'CompareUnit' value we are only setting 'GPT_RTI1_COMP0'. Is it a bug in the GPT MCAL module

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

HI QJ,

I tried the changes you suggested, I see the RTICOMP2 value updated, but 'BQ761xNw1GptCbk()' is triggered from 'Gpt_Ch1Isr' and 'Gpt_Ch2Isr' is not getting triggered, is this expected

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

I saw the RTI interrupt for compare 0/1/2 are enabled:

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Right, after configuring sys_vim.c' i see the 'Gpt_Ch2Isr' getting triggered, but 'BQ761xNw1GptCbk()' is still getting triggered from from 'Gpt_Ch1Isr'

I think we have notification function for each channel ( 'Gpt_ChannelNotifyFunctions' ) but no notification function for each compare unit.

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

Can you share the EB configuration file with me? Which version of EB tresos is used?

0 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 200246 points

I have it: TI_BMS_07_15. But I am not able to open it on EB Tresos 21

0 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 200246 points

Hi Ravi,

Please add one instruction to your main() code to enable RTI compare2 interrupt:

vimREG->REQMASKSET0 |= ((uint32)1U << 4U);

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Hi Q J,

We need to use EB tresos 24 to open the configuration file.

I made the below changes, I am receiving the interrupt Gpt_Ch2Isr, but 'BQ761xNw1GptCbk()' is still getting triggered from from 'Gpt_Ch1Isr' . I see ' 'Gpt_ChannelNotifyFunctions' array size is '2' (maximum channel number).

Regards,

Ravi

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

Ravichandra Sereddy Thipperudra Reddy said:
We need to use EB tresos 24 to open the configuration file.

Do you know where to download EB Tresos 24? I didn't find it in MySecure SW.

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Hi QJ,

Below is the mySecure link

My secure resources | myTI | Texas Instruments

Thanks,

Ravi

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

Thanks, I will check mine.

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Hi QJ,

Were you able to check on this, kindly let me know if you have any updates.

Regards,

Ravi

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

Hi Ravi,

I am lost. Can you tell me what is the issue now?

GPT Config Channel	GptOsTick	BQ761xNw0GptChannel	BQ761xNw1GptChannel
Value	0	1	2
RTI Counter or Gpt Channel ID	0	1	1
RTI Compare Unit	0	1	2
Running Mode	Continuous	One-shot	One-shot
Callback function		BQ761xNw0GptCbk	BQ761xNw1GptCbk
Interrupt	Enabled after calling Gpt_EnableNotification()	Enabled after calling Gpt_EnableNotification()	Enabled after calling Gpt_EnableNotification()
ISR (vim.c)	vPortPreemptiveTick	Gpt_Ch1Isr	Gpt_Ch2Isr

Can you please add a breakpoint in Gpt_Ch1Isr() and Gpt_Ch12Isr() to check if you get the interrupt of RTICOMP1 and RTICOMP2?

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Hi QJ,

I see the 'Gpt_Ch2Isr()' triggered after enabling the interrupt in sys_vim.c

The issue is I don't see 'BQ761xNw1GptCbk' is getting triggered with below changes

The main issue is when Gpt_Ch2Isr() is called it will try to call Gpt_ChannelNotifyFunctions[2] pointer function which is array out of index, so it will crash. I think it is a bug in the GPT.

MAX_GPT_CHANNELS must be 4 instead of 2, and it should contain pointer to call back function for each compare unit.

Regards,

Ravi

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

Hi Ravi,

The compare 2 is used to trigger a wakeup function in CDD project:

and the notification you specified is not called in wakeup function:

0 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 200246 points

Because the compare2 in your case is used as one-shot mode, rather than a wakeup timer, please change the 3rd function to "Gpt_NotifSingleIsr" then try again:

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Hi Q J,

I don't think Gpt_IsrNotifyFunctions array index indicates compare unit instead it is index by the channel mode which is '

Instead, its index is calculated from 'Gpt_IsrIndex[Channel][RTI1_COMPARE2]'

whose value is assigned from the mode configured for compare unit 2, which is 'GPT_CH_MODE_ONESHOT', so the index should be '1', but I see the value is '0', not sure why.

Regards,

Ravi

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

Hi Ravi,

The snapshots are not displayed properly. Can you post them again?

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Posting the images again.

Don't think Gpt_IsrNotifyFunctions array index indicates compare unit instead it is index by the channel mode which is 'ONE SHOT'.

Instead, its index is calculated from 'Gpt_IsrIndex[Channel][RTI1_COMPARE2]'

whose value is assigned from the mode configured for compare unit 2, which is 'GPT_CH_MODE_ONESHOT', so the index should be '1', but I see the value is '0', not sure why.

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

My understanding is that the Gpt_IsrNotifyFunctions is determined by the channel umber, for example BQ761xNw1GptChannel.

If the interrupt is generated by RTI1_COMPARE2, the BQ761xNw1GptChannel is returned value of Gpt_GetConfiguredChannelForCompareUnit(RTI1_COMPARE2);

Gpt_IsrNotifyFunctions is pointing to &Gpt_WakeupContIsr,

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

a) In the 'Gpt_Ch2Isr()' function we can see the index to 'Gpt_IsrNotifyFunctions' array is 'Gpt_IsrIndex[Channel][RTI1_COMPARE2]'

################################################################################

#if ((GPT_CFG_ISR_TYPE == GPT_ISR_CAT1) || (GPT_CFG_ISR_TYPE == GPT_ISR_VOID))
#pragma CODE_STATE(Gpt_Ch2Isr, 32)
/*SAFETYMCUSW 69 S MR:3.4 <INSPECTED> "Reason - To indicate interrupt subroutine" */
#pragma INTERRUPT(Gpt_Ch2Isr, IRQ)
void Gpt_Ch2Isr ( void )
#elif (GPT_CFG_ISR_TYPE == GPT_ISR_CAT2)
ISR( Gpt_Ch2Isr )
#endif
{
uint8 Channel;
Channel = Gpt_GetConfiguredChannelForCompareUnit(RTI1_COMPARE2);
Gpt_IsrNotifyFunctions[Gpt_IsrIndex[Channel][RTI1_COMPARE2]] (Channel);
}

################################################################################

b) In Gpt_StartTimer(), we can see 'Gpt_IsrIndex' values are assigned from channel mode.

################################################################################

/*Set the channel mode for notification index*/
Gpt_IsrIndex[Gpt_Channel][Gpt_Config_pt->ChannelConfig_pt[Gpt_Channel].CompareUnit] = ChannelMode_t;

################################################################################

If we see the value of Gpt_IsrIndex[1][2] is '0'.

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

It should be 1, right?

GPT_CH_MODE_ONESHOT = 1;

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

Yes right it should be 1, I am not sure why its '0'

Also if we enable 'GPT_DEV_ERROR_DETECT' I see 'GPT_E_BUSY', since 'BQ761xNw0GptChannel' and 'BQ761xNw1GptChannel' are assigned to same counter block '1'.

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

I noticed the issue that if 'GPT_DEV_ERROR_DETECT' is enabled (STD_ON) and the RTI counter (0 or 1) has been started, the RTI timer (0 or 1) can not be re-started, and the registers of compare unit used by this channel will not be configured.

Does it work if GPT_DEV_ERROR_DETECT = STD_OFF?

0 Ravichandra Sereddy Thipperudra Reddy over 3 years ago in reply to QJ Wang

TI__Intellectual 860 points

No its not working even when GPT_DEV_ERROR_DETECT = STD_OFF

0 QJ Wang over 3 years ago in reply to Ravichandra Sereddy Thipperudra Reddy

TI__Guru**** 200246 points

Hi Ravi,

I will do a test after I get lab.

0 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 200246 points

The RTI module on Hercules devices has two independent 64 bit counter blocks, and four configurable compare units which are driven by either counter block 0 or counter block 1.

In MCAL driver, the ChannelId of Gpt_ChannelConfigType represents counter clock 0 or counter block 1 (RTI1_CHANNEL1, or RTI1_CHANNEL2). CompareUnit of Gpt_ChannelConfigType represents the compare units (RTI1_COMPARE0, RTI1_COMPARE1, RTI1_COMPARE2, RTI1_COMPARE3).

The RTI can operate in two modes: one-shot mode, and continuous mode. The GPT driver looks like have several restrictions which are not mentioned in user guide.

1. The first restriction for one-shot mode:

The compare unit 0 (RTI1_COMPARE0) can be used as one-shot mode only when It uses counter block 0, and the compare unit 1 (RTI1_COMPARE1) can be used as one-shot mode only when It uses counter block 1.

The Compare unit 2 (RTI1_COMPARE2) and the Compare unit 3 (RTI1_COMPARE3) can not be used as one-shot mode.

If eliminate those restriction, the following changes should be made to Gpt_SetRegStartTimer() function:

For RTI1_CHANNEL1:

For RTI1_CHANNEL2:

0 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 200246 points

2. The 2^nd restriction

If the counter block (RTI1_CHANNEL1, or RTI1_CHANNEL2) is used for one-shot, this counter block can not be used for another one-shot mode, and can not be used for continuous mode.

For example, if both compare unit 0 (RTI1_COMPARE0) and compare unit 1 use counter block 1, and compare unit 0 is configured as one-shot mode, and compare unit 1 is configured as continuous mode mode, when one-shot mode timer is expired, the counter block 1 is stopped and compare unit 1 is also terminated.

To remove this restriction, the following modification should be made to the code in Gpt_NotifSingleIsr():

3. One suggestion for using Gpt_GlobalRestore() in ISR function:

Most of the functions in MCAL driver call Gpt_GlobalSuspend() before the critical code section and Gpt_GlobalRestore() after the critical code section. Normally the Gpt_GlobalSuspend() is to disable the IRQ interrupt, and Gpt_GlobalRestore() is to enable the IRQ interrupt.

The Cortex-R Arch doesn’t support HW nested interrupt. When code enters the IRQ interrupt service routine (ISR), the IRQ interrupt is automatically disabled. The IRQ is automatically re-enabled when the code leaves the ISR. The Gpt_GlobalRestore() call in IRQ or FIQ ISR will cause data abort.

I suggest to comment this line out in ISR:

For example:

Arm-based microcontrollers

Arm-based microcontrollers forum

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