AM2634: AM263x peripheral clock configuration using sysconfig

Hi Bikash, 

Currently the clock configuration is GEL based. Upon connecting to the R5 the gel will execute "Configure_Plls_R5F_400_SYS_200_Clocks()," which calls multiple funciton to achieve an R5 clock of 400MHz and a sysclk of 200MHz. 

In the OnTargetConnect() script we have:

...

        //Configure PLLs
        Configure_Plls_R5F_400_SYS_200_Clocks();

        //Enable all peripheral clocks
        Configure_All_Peripheral_Clks();
    }else{
        GEL_TextOut("Warning !! None of the scripts executed in this mode\n");
    }
}

Where "Configure_Plls_R5F_400_SYS_200_Clocks()" calls for "Program_Core_PLL()" located in "AM263x_PLL.gel":

hotmenu Configure_Plls_R5F_400_SYS_200_Clocks()
{
    if(Enable_OnTarget_Connect == 1){
        Program_Core_PLL();
        Program_Per_PLL();
        Program_SYS_CLK_DIVBY2();
        // Switch R5SS and SYS_CLK to Core PLL, so that R5 run at 400MHz
        Program_R5F_SYS_CLK_SRC();
        GEL_TextOut("\n CLK Programmed R5F=400MHz and SYS_CLK=200MHz \n");
    }else{
        GEL_TextOut("Errrrr... Please Load Gel files\n");
    }
}

hotmenu Program_Core_PLL() 
{
    unsigned int val_pll_core_stat = 0;
    unsigned int val_pll_per_stat = 0;
    unsigned int val_hsdiv_clkout;   

    val_pll_core_stat = Read_MMR(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_STATUS);
    if((val_pll_core_stat & 0x00000400) != 0x00000400)
    {
        // N
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_M2NDIV, 9, 8, 0);
        //M2
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_M2NDIV, 1, 7, 16);
        
        //M
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_MN2DIV, 0x320, 12, 0); 
       
        //N2
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_MN2DIV, 0x0, 4, 16); 

        //SD divider of the PLL with the value of 0x8 to get the optimum jitter performance
        Write_MMR_Field(0x53200418, 8, 8,24);
        
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_CLKCTRL, 0,1, 23);        //Idle

        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_CLKCTRL, 0,1,0);  		//Soft Reset

        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_TENABLE, 1,1,0);          // PLL_CORE_TENABLE = 1;
        
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_CLKCTRL, 1,1,0);          //Soft Reset
        
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_TENABLE, 0,1,0);          // PLL_CORE_TENABLE = 0;
            
        Write_MMR(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_TENABLEDIV, 1);                 // PLL_CORE_TENABLEDIV = 1;
        Write_MMR(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_TENABLEDIV, 0);                 // PLL_CORE_TENABLEDIV = 0;
        
        do
        {     
            val_pll_core_stat = Read_MMR(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_STATUS);
        }while( ((val_pll_core_stat & 0x00000400) != 0x00000400) ) ;
        
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT0, 0x4, 5, 0);//CLKOUT0
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT1, 0x3, 5, 0);//CLKOUT1
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT2, 0x4, 5, 0);//CLKOUT2
        
        
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER, 1,1,2);   // PLL_CORE_HSDIV_TENABLEDIV = 1;
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER, 0,1,2);   // PLL_CORE_HSDIV_TENABLEDIV = 0;
        
        
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT0, 0x1, 1, 8);//CLKOUT0
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT1, 0x1, 1, 8);//CLKOUT1
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT2, 0x1, 1, 8);//CLKOUT1
        
        GEL_TextOut("CORE PLL Configuration Complete \n");
    
    }
}

You can use this script as an example by modifying the M and N dividers as well as the HSDIVIDER values to output the desired values for the output clocks.

Details on the variables used for configuring the PLLs can be found in section 6.4.1.2 Analog Modulesof the TRM. Also, for more detailed instructions on how to configure the Core PLL please refer to section 6.4.1.2.3.1.2 Sequence to Configure the CORE PLL

Best,

Daniel

Link to the TRM: AM263x Sitara Microcontroller Technical Reference Manual (Rev. B) (ti.com)