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I am interfacing a sensor over SPI, and want to stream data for some time before processing it. For this I have setup the DMA for SPI TX and SPI RX, to read out a buffer of 16 bit words, which works as expected.
However, the sensor needs the SS pin to be released and reasserted between each sample using SPI mode 3. When setting up the DMA transfer, the SS pin is set low at the beginning of the transfer, and when the entire buffer is transferred, it is set high again.
From what I can tell from the datasheet, the SSI module has support for pulsing the SS using the FSSHLDFRM bit, but only in 8-bit mode.
Trying to set the FRF bit to set TI Synchronous Serial Frame Format pulses the SS pin during the first clock cycle but it also changes the clock polarity to 0 and does not set the SS high until the beginning of next transfer, so not what I’m looking for.
There is also the advanced mode which looked promising where one could program EOM for every second byte in a 8-bit transfer to simulate 16-bit data, but this can only be used in SPI mode 0.
Is there any functionality I have missed?
Any suggestions to how to achieve a DMA transfer of 16-bit words with SS toggling between each word?
Hello Marte,
I don't believe you've missed any functionality as you are correct about the behavior you've seen for 8-bit mode as well as the limitation of the advanced mode only working for Mode 0.
This is a very specific and unique requirement and I don't believe the device SSI interface is equipped to be able to handle it. From what I understand about your use case, then you will need to forego using the DMA so that instead you can manually control the SS line as a GPIO output to get the required behavior on the SS line.
Best Regards,
Ralph Jacobi
Thank you for the reply, that was what I was afraid of. Will see if I can find another solution to the problem somehow.
I cannot seem to find any timing data of the DMA, how many cycles does an non-incrementing 8bit transfer from memory to a register take from the trigger to the data is moved?
Hello Marte,
The timing data isn't provided because it will vary. The DMA runs secondary to the processor's bus-usage and takes advantage of idle-cycles where the processor isn't using the bus to transfer data. So if the processor is using the bus heavily, it would extend that time beyond the norm and therefore it's not really possible to map out that timing. You'd have to experiment what it looks like for your own application but as I mentioned, I think you will be best of foregoing the DMA entirely so you have precise control.
Best Regards,
Ralph Jacobi