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MSPM0L1306: 32-bit data SPI frame size with MSPM0 L-Series MCU

Part Number: MSPM0L1306

Tool/software:

Hello, good day.

The Technical Reference Manual states that the SPI module has programmable data frame size from 4-bits to 16-bits (Controller Mode).

I need it to see a 32-bit data frame without toggling the Chip Select between the 16-bit data packets.

Is it possible to do this with the PACKEN feature?

Thank you

    • By enabling the PACKEN feature, the SPI module will combine multiple smaller data frames (e.g., two 16-bit frames) into a larger packet.

    • Set the SPI data frame size to 16 bits, which is the maximum supported frame size in this case.

    •  When you send data, the SPI module will automatically pack the data frames into larger packets. For instance, if you need to send a 32-bit data frame, you would send two 16-bit frames consecutively.

    • With PACKEN enabled, the CS signal will remain asserted (active) across the entire transfer of the packed data. This means the CS signal will not toggle between the 16-bit frames, effectively treating the two 16-bit frames as a single 32-bit frame from the perspective of the CS signal.

  • Hello Zain, good day.

    Thank you for the detailed explanation and recommendation.

    The approach that you are describing makes sense to me; I will implement this method and test it. Once I have proven that it, in fact, works; I may share the example and resolve this question.

    Best Regards.

  • You can also use 3 wire mode and control CS yourself.

  • Hello again.

    I have been working on implementing the suggested steps by Zain.

    I am able to see the individual 16-bit data frames. But it appears that the packing feature with the PACKEN = 1 is not working as described in the documentation for the MSPM0 L-Series of MCU.

    While using the debugger features of CCS, I have tracked down the issue to what seems to be related to writing to the TXDATA register of the SPI module.

    The documentation (Technical Reference Manual, doc # slau847d) shows that this is a 32-bit register.

    However when I write a 32-bit value (uint32_t) using the API function calls DL_SPI_transmitDataBlocking32() or even the basic DL_SPI_transmitData32(), what I observe is that only the lower 16-bits of the TXDATA register change while the upper 16-bits remain at zero. This results in only a single 16-bit entry moving to the FIFO, then followed by the 16-bit data frame going out the PICO port. The chip select is only remains active while the 16-bit are transferred out.

    Is there something in the API that truncates the 32-bit value before it gets written to the TXDATA registers since the maximum frame size supported is 16 bits?

    Kind Regards.

  • Hi,

    Sorry for late reply as we have traditional dragon festival.

    The PACKEN can not be set(this is bug, and I will report to our system).

    From the newest TRM, SPI FIFO is 16bit, not 32 bit. So normally SPI can only transmit 16-bit without toggling CS.

    To realize what you want, you can manually control SPI CS pin and didn’t set PACKEN bit.

    . Here is a demo code for you reference: 

    Download link: https://tidrive.ext.ti.com/u/m_TcbXz03EeJ9Nx1/5d29c2cd-0501-4b2e-9f6f-d1009cf38d4b?l

    Access code: RzuiY|69

    N.B.

    Only SPI sending function is test. Receiving function needs further test.

    But there is still a 4 us clock gap between two 16bit operations @ 500k SPI clock.

    As we have discussed offline with your fae, I will close this thread, if you have any question, just give response to our e-mail.

    Regards,

    Zoey