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AM2634: GPMC Addressing Questions

Brad Caldwell
Genius 12595 points
Part Number: AM2634

I'm trying to clarify a couple points with regards to the GPMC memory controller on the AM263x. Specifically, how much memory can be addressed? The datasheet says we can address up to 4MB but based on the number of address lines and data lines for the various modes, we should be able to address much more than that. Need clarifications please. I have a few questions inline below highlighted in red.

AM263x Datasheet

General-Purpose Memory Controller (GPMC)

– 16-bit parallel data bus with 22-bit address bus

– Up to 4MB addressable memory space

Q1) Wouldn't this be 8MB addressable memory?

 

Summary of Table 6-64. GPMC0 Signal Descriptions

GPMC Pin

MuxMode

Non-MuxMode

A21..A11

unused

A21..A11

A10..A1

A26..A17

A10..A1

A0

unused

A0 for 8-bit device

AD15..AD0

A16..1 / D15..D0

D15..D0

 

- 26 address lines

- 16 data lines

- 22 address lines

- 16 data lines

 

Q2) In MuxMode, we have 26 address lines and 16 data lines, wouldn't this be 64M-words (128M-bytes)?

Q3) In non-MuxMode, we have 22 address lines and 16 data lines, wouldn't this be 4M-words (8M-bytes)? This is a repeat of Q1 above

 

AM263x TRM

 

Summary Table 13-165. GPMC Pin Multiplexing Options (don't care about NAND columns)

GPMC Pin

Multiplexed Address Data 32-Bit Device

Multiplexed Address Data 16-bit Device

Non-multiplexed Address Data 16-Bit Device (incomplete 28-bit address range)

Non-multiplexed Address data 8-Bit Device

(incomplete 28-bit address range)

A22..A11

Not used

Not used

A22..A11

A22..A11

A10..A1

Not used

A26..A17

A10..A1

A10..A1

A0

Not used

Not used

Not used

A0

AD31..AD26

           D31..D26

Not used

Not used

Not used

AD25..AD16

A27..A18 / D25..D16

Not used

Not used

Not used

AD15..AD8

A17..A10 / D15..D8

A16..A9 / D15..D8

D15..D8

Not used

AD7..AD0

A9..A2   / D7..D0

A8..A1  / D7..D0

D7..D0

D7..D0

 

26 address lines

32 data lines

26 address lines

16 data lines

22 address lines

16 data lines

23 address lines

8 data lines

Addressable Size

256M-Bytes?

*limited to 128MB

128M-Bytes?

8M-Bytes?

8M-Bytes?

 

Q4) What's wrong with these addressable size calculations based on number of address lines and data lines?

 

*Notes from TRM

  • Even though GPMC supports total address space of 1GB, only 128MB are physically available in this device.
  • GPMC0_DATA 0x00 2000 0000 to 0x00 27FF FFFF 128 MB External memory space region

 

 

Q5) In the figure, it references AD[31-16], those pin names don't exist, assuming these are A[31-16].

 

 

  • 0
    TI__Expert 7630 points

    Hi Brad,

    I believe the confusion stems from the fact that the datasheet does not specify that the addressable 4MB apply to a non-muxed mode of operation where you only have 22 address lines since data lines are not multiplexed between address and data. However, in a non-muxed mode with 23 address lines and 8-bit data you would be right about 8MB being the maximum addressable range in non-muxed mode. Going through your questions:

    Q1-Q3) Assuming this is non-muxed mode of operation then 4MB is correct. 2^22 = 4MB addressable range. Data lines are not taken in account in this case for the reason explained above

    Q2) You are correct in this one 26-bit address and 16-bit word --> (2^26) * 2 bytes = 128MB

    Q4) 

    Q5) Yes correct, these pin names don't exist. The picture is referencing the fact that these top 16-bits of the address range will be multiplexed between address and data lines as this is a block diagram of an AD-muxed memory operation. I do see why this could be confusing, I will work to make this block diagram more comprehensible in future revisions of the TRM

    Below is also a post addressing a similar question for the AM64 device that I think you could use as a reference for understanding better the addressing ranges in the different GPMC mode. AM263x and AM64x share the same GPMC IP so the answer Mark gave is also applicable in this case:

    AM6442: GPMC non-multiplexed address data - Processors forum - Processors - TI E2E support forums

    I hope this information helps, please do not hesitate to reach out if you have any more questions.

    Best,

    Daniel

  • 0 in reply to Daniel Bermudez
    TI__Genius 12595 points

    Daniel,

    Thanks for the responses. If you don't mind I have a couple follow-up comments/questions, just need to be certain before doing a board design. Can you confirm the following

    1) The entire GPMC address space (all four chip selects combined) is 128MB as defined by the memory map.

    2) For the various modes, here are the max memory sizes we could have on a single chip select.

    • Using Multiplexed Address Data 32-Bit Device, we could have up to 128MB on a single chip select. 
    • Using Multiplexed Address Data 16-bit Device, we could have up to 128MB on a single chip select. 
    • Using Non-multiplexed Address Data 16-Bit Device, we could have up to 4MB on a single chip select. **
    • Using Non-multiplexed Address data 8-Bit Device, we could have up to 8MB on a single chip select.

    ** I'm still not clear why we're limited to 4MB in the non-muxed 16-bit device mode? 

    Thanks

  • +1 in reply to Brad Caldwell
    TI__Expert 7630 points

    Hi Brad,

    Brad Caldwell said:
    1) The entire GPMC address space (all four chip selects combined) is 128MB as defined by the memory map.

    Correct, this space is shared between all four chip selects

    Brad Caldwell said:

    2) For the various modes, here are the max memory sizes we could have on a single chip select.

    • Using Multiplexed Address Data 32-Bit Device, we could have up to 128MB on a single chip select. 
    • Using Multiplexed Address Data 16-bit Device, we could have up to 128MB on a single chip select. 
    • Using Non-multiplexed Address Data 16-Bit Device, we could have up to 4MB on a single chip select. **
    • Using Non-multiplexed Address data 8-Bit Device, we could have up to 8MB on a single chip select.

    ** I'm still not clear why we're limited to 4MB in the non-muxed 16-bit device mode? 

    The 16-bit non-muxed mode doesn't actually use all 23 available address lines in the device as A0 remains unused, leaving you with 22 address lines instead of the 23 you would need to access a full 8MB region of memory. TRM shows the following:

    the footnote for Table 13-165 explains that A0 is only used to effectively address 8-bit devices on non-multiplexed memories since it acts as a devices system byte address line. You can find more information on this in the first bullet point of section 13.3.1.4.7.1 Chip-Select Base Address and Region Size of the TRM:

    Having 22 address lines would only let you access 4MB in a non-multiplexed protocol.  2^22 = 4MB addressable range.

    Hope this helps clear things up.

    Best,

    Daniel