MCU-PLUS-SDK-AM273X: Ethernet package loss during ping when adding Ethernet Bare metal to SBL with RMII PHY

Hi Chris,

Can you please share the debug statistics, for steps follow : (+) [FAQ] MCU-PLUS-SDK-AM243X: How do I get CPSW diagnostic statistics using debug gels in MCU+ SDK Enet LLD? - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Let me get back to you after discussion from internl team.

BR

Nilabh A.

Nilabh,

Thanks for sharing the link. This is helpful. 

For customer's problem, based on their test, I think the RMII PHY setting is ok as similar setting in old eth driver can work ok.

May the problem be caused by some change on PHY state machine in latest ethernet driver or other related part as customer is using RMII PHY which is not same as the one (RGMII) on AM2732 EVM?

Thanks,

Chris

HI Chris,

Let me get back with delta in phy state machine implementation from internal team

BR

Nilabh A.

HI Chris,

Apologies for the delay, our internal expert is on leave, He is not back yet. I will get back on this thread as soon as I have some info.

BR
Nilabh A.

Nilabh,

Is the expert back? Any update?

Thanks,

Chris

Hi Chris,

We have few question from expert:(From 8.4 working scenario)

1. Are we talking about two boards (evm or custom board), please share the details of phy they are using? 

2. Were they using LwIP stack/ or any other stack.

3. Which side do they see the packet loss (Tx or RX side)?

4. Have they made changes in event function which sends/receive packets? Also please try to increase buffer size(via syscfg) and try again.

Chris Meng said:

other related part as customer is using RMII PHY which is not same as the one (RGMII) on AM2732 EVM

This can be very likely be the case. We will need more information here to root cause the issue.

Also can you please share application logs and syscfg file from both 8.5 and 8.4 SDK version which they were/are using.

1、We use RTL8201.

2、We use SDK 8.5 LwIP stack.

3、Only test ping packet loss, 2732 side packet loss, the specific TX/RX side packet loss is not determined.

4、The network correlation in syscfg is as follows. Add how to modify buffsize in syscfg.

enet_cpsw1.$name = "CONFIG_ENET_CPSW0";
enet_cpsw1.RtosVariant = "NoRTOS";
enet_cpsw1.AppLinkUpPortMask = "ALL_PORTS";
enet_cpsw1.PktInfoOnlyEnable = true;
enet_cpsw1.LargePoolPktCount = 192;
enet_cpsw1.txDmaChannel[0].$name = "ENET_DMA_TX_CH0";
enet_cpsw1.rxDmaChannel[0].$name = "ENET_DMA_RX_CH0";
enet_cpsw1.rxDmaChannel[0].PacketsCount = 192;
enet_cpsw1.pinmux[0].$name = "ENET_CPSW_PINMUX0";
enet_cpsw1.netifInstance.create(1);
enet_cpsw1.netifInstance[0].$name = "NETIF_INST_ID0";

enet_cpsw1.pinmux[0].MSS_MDIO.$suggestSolution = "MSS_MDIO0";
enet_cpsw1.pinmux[0].MSS_MDIO.DATA.$suggestSolution = "ball.P19";
enet_cpsw1.pinmux[0].MSS_MDIO.CLK.$suggestSolution = "ball.R19";
enet_cpsw1.pinmux[0].MSS_RMII.$suggestSolution = "MSS_RMII0";
enet_cpsw1.pinmux[0].MSS_RMII.RXD0.$suggestSolution = "ball.P18";
enet_cpsw1.pinmux[0].MSS_RMII.RXD1.$suggestSolution = "ball.N19";
enet_cpsw1.pinmux[0].MSS_RMII.RXER.$suggestSolution = "ball.F18";
enet_cpsw1.pinmux[0].MSS_RMII.TXD0.$suggestSolution = "ball.L18";
enet_cpsw1.pinmux[0].MSS_RMII.TXD1.$suggestSolution = "ball.L17";
enet_cpsw1.pinmux[0].MSS_RMII.DV.$suggestSolution = "ball.F16";
enet_cpsw1.pinmux[0].MSS_RMII.REFCLK.$suggestSolution = "ball.E19";
enet_cpsw1.pinmux[0].MSS_RMII.TXEN.$suggestSolution = "ball.J18";

Hi Gmsy,

Could you please attach application log also.

BR

Nilabh A.

Starting QSPI Bootloader ... 
Enet_open: cpsw2g: features: 0x00000002
Enet_open: cpsw2g: errata  : 0x00000000
EnetPhy_setNextState: PHY 3: INIT -> FINDING (20 ticks)
EnetPhy_setNextState: PHY 3: FINDING -> FOUND (0 ticks)
?"$N??F?? ?$?dReg: PHY 3: reg 2 val 0x001c ??F
         ??
           ��"I �C?
EnetPhy_readReg: PHY 3: reg 3 val 0xc816 ??"
EnetPhy_bindDriver: PHY 3: OUI:000732 Model:01 Ver:06 <-> 'dp83867'
EnetPhy_bindDriver: PHY 3: OUI:000732 Model:01 Ver:06 <-> 'generic'
EnetPhy_bindDriver: PHY 3: OUI:000732 Model:01 Ver:06 <-> 'generic' : OK
EnetPhy_open: PHY 3: open
PHY 0 is alive
PHY 3 is alive
Starting lwIP, local interface IP is dhcp-enabled
Host MAC address-0 : 70:ff:76:1d:ec:f2
[LWIPIF_LWIP] NETIF INIT SUCCESS
Enet IF UP Event. Local interface IP:10.10.10.155
GenericPhy_reset: PHY 3: reset
EnetPhy_rmwReg: PHY 3: read reg 0 val 0x3100
EnetPhy_rmwReg: PHY 3: write reg 0 val 0xb100
EnetPhy_setNextState: PHY 3: FOUND -> RESET_WAIT (10 ticks)
EnetPhy_readReg: PHY 3: reg 0 val 0x1000 ?? ??d
GenericPhy_isResetComplete: PHY 3: reset is complete
EnetPhy_setNextState: PHY 3: RESET_WAIT -> ENABLE (0 ticks)
EnetPhy_enableState: PHY 3: enable
EnetPhy_rmwReg: PHY 3: read reg 0 val 0x1000
EnetPhy_rmwReg: PHY 3: write reg 0 val 0x1000
EnetPhy_enableState: PHY 3: req caps: FD1000 HD1000 FD100 HD100 FD10 HD10 
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?/ 
EnetPhy_enableState: PHY 3: PHY caps: FD100 HD100 FD10 HD10 
EnetPhy_enableState: PHY 3: MAC caps: FD100 HD100 FD10 HD10 
EnetPhy_enableState: PHY 3: refined caps: FD100 HD100 FD10 HD10 
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 w0 
EnetPhy_enableState: PHY 3: PHY is NWAY-capable
EnetPhy_enableState: PHY 3: setup NWAY
EnetPhy_setupNway: PHY 3: NWAY advertising: FD100 HD100 FD10 HD10 
EnetPhy_setupNway: PHY 3: config is needed
EnetPhy_rmwReg: PHY 3: read reg 4 val 0x01e1
EnetPhy_rmwReg: PHY 3: write reg 4 val 0x01e1
EnetPhy_setupNway: PHY 3: restart autonegotiation
EnetPhy_rmwReg: PHY 3: read reg 0 val 0x1000
EnetPhy_rmwReg: PHY 3: write reg 0 val 0x1000
EnetPhy_rmwReg: PHY 3: read reg 0 val 0x1000
EnetPhy_rmwReg: PHY 3: write reg 0 val 0x1300
EnetPhy_setNextState: PHY 3: ENABLE -> NWAY_START (50 ticks)
EnetPhy_readReg: PHY 3: reg 0 val 0x1000 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ??"
EnetPhy_setNextState: PHY 3: NWAY_START -> NWAY_WAIT (80 ticks)
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x7849 ?? ??d
EnetPhy_readReg: PHY 3: reg 1 val 0x786d ?? ??d
EnetPhy_readReg: PHY 3: reg 4 val 0x01e1 6
EnetPhy_readReg: PHY 3: reg 5 val 0x4de1 ??"
EnetPhy_findCommonCaps: PHY 3: local caps: FD100 HD100 FD10 HD10 
EnetPhy_findCommonCaps: PHY 3: partner caps: FD100 HD100 FD10 HD10 
EnetPhy_findCommonCaps: PHY 3: common caps: FD100 HD100 FD10 HD10 
EnetPhy_findCommonNwayCaps: PHY 3: common caps: FD100 HD100 FD10 HD10 
EnetPhy_nwayWaitState: PHY 3: negotiated mode: 100 Mbps full-duplex
EnetPhy_setNextState: PHY 3: NWAY_WAIT -> LINKED (0 ticks)
Cpsw_handleLinkUp: Port 1: Link up: 100-Mbps Full-Duplex
MAC Port 1: link up
Network Link UP Event
Network is UP ...--=_mixed 0037436448258950_=--

Start printing as attachment，thanks.

Thanks Gmsy,

Let me get back with the analysis here.

BR

Hi Gmsy,

Few issue that are very apparent here:

1. How many phys do you have on your custom board, It seems you have two, but second one(other than dp83867) is not registered by enet driver. Do you have the phy driver for the RMII phy?

2. Can you try a layer 2 example on your custom board and see if there are any issues(like packet drops) ?>

3. Please check LWIPIF configuration in syscfg and increase the pool size. and see if you still see the packet drops.

Also please how do you do your ping test?

BR

Nilabh A.

1.Our board has only one phy. The printing in the log is as follows “EnetPhy_bindDriver: PHY 3: OUI:000732 Model:01 Ver:06 <-> 'generic' : OK”，generic_phy.c is used.

2.Which two examples are you talking about?

3.Refers to PacketPoolConfig in sysconfig? Large Pool Packet Size is 1536,Medium Pool Packet Size is 512,Small Pool Packet Size is 128, This is problematic.

Gmsy Bryant said:

Our board has only one phy.

As I can see from the conversation earlier you are using a RMII Phy, can you please tell me the name of phy. Do you have corresponding driver for the same?

Gmsy Bryant said:

.Which two examples are you talking about?

I was referring to layer 2 cpsw example: AM273x MCU+ SDK: Enet Layer 2 Multi-Channel Example

Gmsy Bryant said:

This is problematic.

Can you please elaborate this one?

1. The name of phy is RTL8201，We have used this chip on other platforms. Under Linux, it can work directly without configuring its registers.

Can we get all the registers of phy? How to get it in the code？I want to see if the register value has obvious exceptions.

2.I tried to run.

3.Consistent with the previous phenomenon, ping packet loss is serious.

Hi Gmsy,

Can you please get the following debug stats for us to root cause the issue:

1. Please follow this and get the debug stats: (+) [FAQ] MCU-PLUS-SDK-AM243X: How do I get CPSW diagnostic statistics using debug gels in MCU+ SDK Enet LLD? - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

I want to see phy's register and use cpsw_ mdio_ Print in config.gel_ phy_ Reg function, but found # define CPSW defined in. gel_ 2G_ MDIO_ BASE_ The ADDR is wrong. It is changed to 0x07000000 in am2732; The reading is blocked. Please help to see why,thanks.

Hi Gmsy,

Let me check on this and get back to you by EOD

Nilabh,

Any update?

Thanks,

Chris

Hi Chris,

I am still working on this, we are able to see the statistics for AM273 devices by modifying the base address in gels script. I will try to share the gel script by tomorrow.

/cfs-file/__key/communityserver-discussions-components-files/908/AM273x_5F00_gels.zip

Please find the gel files for Am273x and share the debug stats that you see on your device.

Br
Nilabh A.

Our environment is currently unable to debug sbl through a CCS connection, so I tried to change the sbl project to an app to run and obtain the phy register value, and found that the ping package was not lost.

Therefore, in the same project code, combine cmd and makefile_ ccs_ bootimage_ Modifying gen to sbl ping has a high probability of packet loss; Modifying to an app does not cause packet loss. Can this information provide some positioning assistance?

Update the replication situation. When the SBL compiler is modified to an app, there is still a ping packet loss when burning it to the board and running it; No packet loss occurs during direct ccs connection debugging.

file.zip

To reiterate the current situation, the same project (SBL has no freertos and network functionality). Compile into SBL, burn to flash for operation, ping for packet loss; Compile into an app, burn to flash, and use SBL_ QSPI boot operation, ping without packet loss. 

There are two folders in the attachment, where "sbl" refers to the files used for compiling into sbl, and "app" refers to the files used for compiling into an app.