• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 811 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

AM263x SPI Chip-select TCS issue

AM263x SPI Chip-select TCS issue

Gianni Perugini
Prodigy 130 points
Other Parts Discussed in Thread: SYSCONFIG, AM2634

Hi Erik,

based on your reply in my previous thread:

"I cannot provide exact measurements at this point but the delay that is being observed is due to software overhead involved with the interrupts being used to drive the example. The half clock cycle TCS value can be true while not being observed in this example as it is a hardware specification. Is there a specific value for the delay between CS and first clock cycle that you are trying to achieve?

EDIT: It is possible to get a half clock cycle delay with the AM263x CC and the MCSPI Loopback demo. There are two SYSCONFIG configurations needed:

1) Set mode of operation to Multi Master

2) Set Operating mode to polled mode"

Why should we set polled mode?

We are using FreeRTOS operative system and if we use a polled function we have to block a task in polling mode. We prefer to use the Interrupt mode on SPI management.

It's seem to us that you suggested a workaround. 

Could it be a possible silicon bug on Sitara AM2634?

Waiting for your kind reply

Thanks

BR

Gianni

  • 0
    TI__Expert 6835 points

    Hello Gianni,

    Polled mode reduces the interrupt service routine call delay which, in turn, will reduce the CS assertion to first clock. If the ISR call delay is longer than a half clock cycle, then the delay between CS assertion and first clock will be longer than a half clock cycle regardless of the TCS value. I have not tested to observe if the McSPI Loopback example in Multi Master mode of operation and Interrupt Mode as the Operating mode yields a half-clock cycle delay between CS and first clock. I will be able to test this on Monday. 

    Regards,

    Erik

  • 0 in reply to Erik Friedel
    Prodigy 130 points

    Hi Erik,

    Erik Friedel said:
    I will be able to test this on Monday

    ok thanks. I'll wait for your result. 

    Thanks

    BR

    Gianni

  • 0 in reply to Gianni Perugini
    TI__Expert 6835 points

    Hello Gianni,

    In Interrupt Mode, when the mode of operation is Multi-Master, then the delay between CS and First clock is confirmed to be a half clock cycle (10ns) as set by the TCS value. Please let me know if you have any additional questions.

    Regards,

    Erik