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Hi,
I'm trying to see if it's possible to access the MSRAM from M4F core.
As far as I understand there should be a way to access it using RAT module, but I'm unsure how exactly.
Any example code would be appreciated.
thanks in advance
Hi Martin,
Direct access to MSRAM memory from M4 core works. You don't need to use RAT for the same.
I tried the same and attached the patch for the same on a SBL-NULL.
/cfs-file/__key/communityserver-discussions-components-files/908/test_5F00_m4_5F00_access.patch
Hope this helps.
Best Regards,
Aakash
Thank you! this is wonderful and it does work.
and I think I can see what didn't work for me, what I'm trying to do is write data with r5 and read it with m4. but now that I can confirm the access works, when I look at memory view from both cores, the r5 has my data written to it, but m4 can't see them.
Could this be because the data is stored in r5's cache so it's not actually in the ram?
I don't have experience with how arm does caching, only x86-64.
Is there any flush cache instruction??
Hi martin salko,
This can be possible.
Cortex M4F does not have any cache memory whereas R5F cores have 32KB of I-Cache and 32KB of D-Cache memory.
Use this command in R5F Application post writing.