This a continuation of the original issue, 1185701.
Summary: using mcu_plus_sdk_am64x_08_03_00_18, modify examples/drivers/gpio/gpio_input_interrupt/ to use MCU_GPIO0_21 pin as interrupt source. I'm using this version of SDK because later versions don't have board.c. I need board.c in order to setup to use MCU GPIO interrupt router, and I don't see how to do this using sysconfg.
I modified TISCI SYSFW to allow routing of MCU_GPIO0_x interrupts to R5FSS_0_0 core. These interrupts would otherwise be routed to the M4 core.
I see in board.c:Sciclient_rmIrqSet() that the interrupt route setup is sucessful. I see that MCU_GPIO0_21 is toggling and I can correctly read the state of the pin. Interrupts should be happening, but they don't.
Can you provide a working example of interrupt code for R5 from MCU_GPIO0_x? Can you check over the attached files?
/*
* K3 System Firmware Resource Management Configuration Data
* Auto generated from K3 Resource Partitioning tool
*
* Copyright (c) 2018-2020, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* \file V3/sciclient_defaultBoardcfg.c
*
* \brief File containing the tisci_boardcfg default data structure to
* send TISCI_MSG_BOARD_CONFIG message.
*
*/
/* ========================================================================== */
/* Include Files */
/* ========================================================================== */
#include <drivers/sciclient.h>
#include <drivers/sciclient/include/tisci/am64x_am243x/tisci_hosts.h>
#include <drivers/sciclient/include/tisci/am64x_am243x/tisci_boardcfg_constraints.h>
#include <drivers/sciclient/include/tisci/am64x_am243x/tisci_devices.h>
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
/* \brief Structure to hold the RM board configuration */
struct tisci_local_rm_boardcfg {
struct tisci_boardcfg_rm rm_boardcfg;
/**< Board configuration parameter */
struct tisci_boardcfg_rm_resasg_entry resasg_entries[TISCI_RESASG_ENTRIES_MAX];
/**< Resource assignment entries */
};
const struct tisci_local_rm_boardcfg gBoardConfigLow_rm
__attribute__(( aligned(128), section(".boardcfg_data") )) =
{
.rm_boardcfg = {
.rev = {
.tisci_boardcfg_abi_maj = TISCI_BOARDCFG_RM_ABI_MAJ_VALUE,
.tisci_boardcfg_abi_min = TISCI_BOARDCFG_RM_ABI_MIN_VALUE,
},
.host_cfg = {
.subhdr = {
.magic = TISCI_BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
.size = (uint16_t) sizeof(struct tisci_boardcfg_rm_host_cfg),
},
.host_cfg_entries = {
{
.host_id = TISCI_HOST_ID_A53_2,
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
.allowed_orderid = 0xAAAAAAAA,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
{
.host_id = TISCI_HOST_ID_M4_0,
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
.allowed_orderid = 0xAAAAAAAA,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
{
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
.allowed_orderid = 0xAAAAAAAA,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
{
.host_id = TISCI_HOST_ID_MAIN_0_R5_3,
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
.allowed_orderid = 0xAAAAAAAA,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
{
.host_id = TISCI_HOST_ID_MAIN_1_R5_1,
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
.allowed_orderid = 0xAAAAAAAA,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
{
.host_id = TISCI_HOST_ID_MAIN_1_R5_3,
.allowed_atype = 0b101010,
.allowed_qos = 0xAAAA,
.allowed_orderid = 0xAAAAAAAA,
.allowed_priority = 0xAAAA,
.allowed_sched_priority = 0xAA
},
},
},
.resasg = {
.subhdr = {
.magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
.size = (uint16_t) sizeof(struct tisci_boardcfg_rm_resasg),
},
.resasg_entries_size = 176 * sizeof(struct tisci_boardcfg_rm_resasg_entry),
},
},
.resasg_entries = {
{
.num_resource = 16,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 0,
.host_id = TISCI_HOST_ID_A53_2,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 16,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 16,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 20,
.host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 24,
.host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 28,
.host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
.num_resource = 8,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_CMP_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 32,
.host_id = TISCI_HOST_ID_ALL,
},
{
.num_resource = 8,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 0,
.host_id = TISCI_HOST_ID_A53_2,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 8,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 8,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 10,
.host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 12,
.host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 14,
.host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 0,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0, // this is like regular GPIO
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 0,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1, // same as MAIN_0_R5_0?
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 2,
.host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
.num_resource = 41,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_TIMESYNC_EVENT_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 0,
.host_id = TISCI_HOST_ID_ALL,
},
{
.num_resource = 136,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
.start_resource = 50176,
.host_id = TISCI_HOST_ID_ALL,
},
{
.num_resource = 1,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
.start_resource = 0,
.host_id = TISCI_HOST_ID_ALL,
},
{
.num_resource = 12,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
.start_resource = 0,
.host_id = TISCI_HOST_ID_A53_2,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
.start_resource = 12,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
.start_resource = 12,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
.start_resource = 18,
.host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
.start_resource = 20,
.host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
.start_resource = 24,
.host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
.num_resource = 1,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
.start_resource = 26,
.host_id = TISCI_HOST_ID_M4_0,
},
{
.num_resource = 1,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
.start_resource = 27,
.host_id = TISCI_HOST_ID_ALL,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
.start_resource = 48,
.host_id = TISCI_HOST_ID_A53_2,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
.start_resource = 54,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
.start_resource = 54,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
.start_resource = 60,
.host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
.start_resource = 62,
.host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
.start_resource = 66,
.host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
.start_resource = 28,
.host_id = TISCI_HOST_ID_A53_2,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
.start_resource = 34,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
.start_resource = 34,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
.start_resource = 40,
.host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
.start_resource = 42,
.host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
.start_resource = 46,
.host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
.num_resource = 12,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
.start_resource = 0,
.host_id = TISCI_HOST_ID_A53_2,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
.start_resource = 12,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
.start_resource = 12,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
.start_resource = 18,
.host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
.start_resource = 20,
.host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
.start_resource = 24,
.host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
.num_resource = 1,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
.start_resource = 26,
.host_id = TISCI_HOST_ID_M4_0,
},
{
.num_resource = 1,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
.start_resource = 27,
.host_id = TISCI_HOST_ID_ALL,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
.start_resource = 0,
.host_id = TISCI_HOST_ID_A53_2,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
.start_resource = 6,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
.start_resource = 6,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
.start_resource = 12,
.host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
.start_resource = 14,
.host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
.start_resource = 18,
.host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
.start_resource = 0,
.host_id = TISCI_HOST_ID_A53_2,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
.start_resource = 6,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 6,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
.start_resource = 6,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
.start_resource = 12,
.host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
.start_resource = 14,
.host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
.start_resource = 18,
.host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
.num_resource = 36,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
.start_resource = 4,
.host_id = TISCI_HOST_ID_A53_2,
},
{
.num_resource = 14,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
.start_resource = 44,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 14,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
.start_resource = 44,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 14,
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{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
.start_resource = 9,
.host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
.start_resource = 13,
.host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
.num_resource = 1,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
.start_resource = 15,
.host_id = TISCI_HOST_ID_M4_0,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
.start_resource = 0,
.host_id = TISCI_HOST_ID_A53_2,
},
{
.num_resource = 3,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
.start_resource = 4,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 3,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
.start_resource = 4,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
.start_resource = 7,
.host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
.start_resource = 9,
.host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
.start_resource = 13,
.host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
.num_resource = 1,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
.start_resource = 15,
.host_id = TISCI_HOST_ID_M4_0,
},
{
.num_resource = 1,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
.start_resource = 16,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 1,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
.start_resource = 16,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 16,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
.start_resource = 16,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 16,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
.start_resource = 16,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 8,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN),
.start_resource = 32,
.host_id = TISCI_HOST_ID_ALL,
},
{
.num_resource = 8,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN),
.start_resource = 32,
.host_id = TISCI_HOST_ID_ALL,
},
{
.num_resource = 1,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN),
.start_resource = 19,
.host_id = TISCI_HOST_ID_ALL,
},
{
.num_resource = 8,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN),
.start_resource = 40,
.host_id = TISCI_HOST_ID_ALL,
},
{
.num_resource = 1,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN),
.start_resource = 20,
.host_id = TISCI_HOST_ID_ALL,
},
{
.num_resource = 8,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN),
.start_resource = 40,
.host_id = TISCI_HOST_ID_ALL,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
.start_resource = 21,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
.start_resource = 21,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 64,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
.start_resource = 48,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 64,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
.start_resource = 48,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
.start_resource = 25,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
.start_resource = 25,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 64,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
.start_resource = 112,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 64,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
.start_resource = 112,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 1,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
.start_resource = 0,
.host_id = TISCI_HOST_ID_ALL,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_VIRTID),
.start_resource = 2,
.host_id = TISCI_HOST_ID_A53_2,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
.start_resource = 20,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
.start_resource = 20,
.host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
.start_resource = 22,
.host_id = TISCI_HOST_ID_MAIN_0_R5_3,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
.start_resource = 24,
.host_id = TISCI_HOST_ID_MAIN_1_R5_1,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
.start_resource = 26,
.host_id = TISCI_HOST_ID_MAIN_1_R5_3,
},
{
.num_resource = 4,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
.start_resource = 28,
.host_id = TISCI_HOST_ID_ALL,
},
}
};
/*
* Copyright (C) 2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <kernel/dpl/DebugP.h>
#include <kernel/dpl/ClockP.h>
#include <kernel/dpl/AddrTranslateP.h>
#include <kernel/dpl/HwiP.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"
/*
* This example configures a GPIO pin in input mode
* and configures it to generate interrupt on rising edge.
* The application waits for 5 interrupts, prints the
* number of interrupts and exits.
*/
uint32_t gGpioBaseAddr = (CSL_MCU_GPIO0_BASE); // 0x4201000 + 0x1000
HwiP_Object gGpioHwiObject;
volatile uint32_t gGpioIntrDone = 0;
static void GPIO_bankIsrFxn(void *args);
extern void Board_gpioInit(void);
extern void Board_gpioDeinit(void);
extern uint32_t Board_getGpioIntrNum(void);
extern uint32_t Board_getGpioNum(void);
void gpio_input_interrupt_main(void *args)
{
int32_t retVal;
uint32_t pinNum, intrNum;
uint32_t bankNum, waitCount = 5;
HwiP_Params hwiPrms;
/* Open drivers to open the UART driver for console */
Drivers_open();
Board_driversOpen();
Board_gpioInit();
DebugP_log("GPIO Input Interrupt Test Started ...\r\n");
DebugP_log("GPIO Interrupt Configured for Rising Edge ...\r\n");
pinNum = 21;
intrNum = Board_getGpioIntrNum();
bankNum = GPIO_GET_BANK_INDEX(pinNum);
/* Address translate */
gGpioBaseAddr = (uint32_t) AddrTranslateP_getLocalAddr(gGpioBaseAddr);
/* Setup GPIO for interrupt generation */
GPIO_setDirMode(gGpioBaseAddr, pinNum, GPIO_DIRECTION_INPUT);
GPIO_setTrigType(gGpioBaseAddr, pinNum, GPIO_TRIG_TYPE_FALL_EDGE);
GPIO_bankIntrEnable(gGpioBaseAddr, bankNum);
/* Register pin interrupt */
HwiP_Params_init(&hwiPrms);
hwiPrms.intNum = intrNum;
hwiPrms.callback = &GPIO_bankIsrFxn;
hwiPrms.args = (void *) pinNum;
retVal = HwiP_construct(&gGpioHwiObject, &hwiPrms);
DebugP_assert(retVal == SystemP_SUCCESS );
DebugP_log("Generate interrupts to trigger GPIO interrupt ...\r\n", Board_getGpioNum());
while(gGpioIntrDone < waitCount)
{
/* Keep printing the current GPIO value */
DebugP_log("Interrupted %d times(bank %d, val %x)\r\n",
gGpioIntrDone, bankNum, GPIO_pinRead(gGpioBaseAddr, pinNum));
ClockP_sleep(1);
}
DebugP_log("Interrupted %d times\r\n", gGpioIntrDone);
/* Unregister interrupt */
GPIO_bankIntrDisable(gGpioBaseAddr, bankNum);
GPIO_setTrigType(gGpioBaseAddr, pinNum, GPIO_TRIG_TYPE_NONE);
GPIO_clearIntrStatus(gGpioBaseAddr, pinNum);
HwiP_destruct(&gGpioHwiObject);
DebugP_log("GPIO Input Interrupt Test Passed!!\r\n");
DebugP_log("All tests have passed!!\r\n");
Board_gpioDeinit();
Board_driversClose();
Drivers_close();
}
static void GPIO_bankIsrFxn(void *args)
{
uint32_t pinNum = (uint32_t) args;
uint32_t bankNum = GPIO_GET_BANK_INDEX(pinNum);
uint32_t intrStatus, pinMask = GPIO_GET_BANK_BIT_MASK(pinNum);
/* Get and clear bank interrupt status */
intrStatus = GPIO_getBankIntrStatus(gGpioBaseAddr, bankNum);
GPIO_clearBankIntrStatus(gGpioBaseAddr, bankNum, intrStatus);
gGpioIntrDone++;
/* Per pin interrupt handling */
if(intrStatus & pinMask)
{
}
}
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <drivers/hw_include/cslr_soc.h>
#include <drivers/gpio.h>
#include <drivers/sciclient.h>
#include "ti_drivers_config.h"
/*
* Board info
*/
/* This is based on DMSC board config and core */
#define BOARD_GPIO_INTR_NUM (CSLR_R5FSS0_CORE0_INTR_MCU_MCU_GPIOMUX_INTROUTER0_OUTP_0)
#define BOARD_GPIO_NUM (21)
#define GPIO_PIN BOARD_GPIO_NUM
/** \brief bank interrupt source index base */
#define TISCI_BANK_SRC_IDX_BASE_GPIO0 (0U)
#define TISCI_BANK_SRC_IDX_BASE_GPIO1 (90U)
#define TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 (0U)
static void Sciclient_gpioIrqSet(void);
static void Sciclient_gpioIrqRelease(void);
void Board_gpioInit(void)
{
Sciclient_gpioIrqSet();
}
void Board_gpioDeinit(void)
{
Sciclient_gpioIrqRelease();
}
uint32_t Board_getGpioIntrNum(void)
{
return (BOARD_GPIO_INTR_NUM);
}
uint32_t Board_getGpioNum(void)
{
return (BOARD_GPIO_NUM);
}
static void Sciclient_gpioIrqSet(void)
{
int32_t retVal;
struct tisci_msg_rm_irq_set_req rmIrqReq;
struct tisci_msg_rm_irq_set_resp rmIrqResp;
/* For setting the IRQ for GPIO using sciclient APIs, we need to populate
* a structure, tisci_msg_rm_irq_set_req instantiated above. The definition
* of this struct and details regarding the struct members can be found in
* the tisci_rm_irq.h.
*/
/* Initialize all flags to zero since we'll be setting only a few */
rmIrqReq.valid_params = 0U;
/* Our request has a destination id, so enable the flag for DST ID */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
/* DST HOST IRQ is the output index of the interrupt router. We need to make sure this is also enabled as a valid param */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
/* This is not a global event */
rmIrqReq.global_event = 0U;
/* Our interrupt source would be the GPIO peripheral. The source id has to be a device id recognizable by the SYSFW.
* The list of device IDs can be found in tisci_devices.h file under source/drivers/sciclient/include/tisci/am64x_am243x/.
* In GPIO case there are 3 possible options - TISCI_DEV_GPIO0, TISCI_DEV_GPIO1, TISCI_DEV_MCU_GPIO0. For input interrupt,
* we need to choose the TISCI_DEV_GPIO1
*/
rmIrqReq.src_id = TISCI_DEV_MCU_GPIO0;
/* This is the interrupt source index within the GPIO peripheral */
rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 + GPIO_GET_BANK_INDEX(GPIO_PIN);
/* This is the destination of the interrupt, usually a CPU core. Here we choose the TISCI device ID for R5F0-0 core.
* For a different core, the corresponding TISCI device id has to be provided */
rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0;
/* This is the output index of the interrupt router. This depends on the core and board configuration */
rmIrqReq.dst_host_irq = Board_getGpioIntrNum();
/* Rest of the struct members are unused for GPIO interrupt */
rmIrqReq.ia_id = 0U;
rmIrqReq.vint = 0U;
rmIrqReq.vint_status_bit_index = 0U;
rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
/* To set the interrupt we now invoke the Sciclient_rmIrqSet function which
* will find out the route to configure the interrupt and request DMSC to
* grant the resource
*/
retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);
DebugP_log("Sciclient_rmIrqSet = %d\n", retVal);
if(0 != retVal)
{
DebugP_log("[Error] Sciclient event config failed!!!\r\n");
DebugP_assert(FALSE);
}
return;
}
static void Sciclient_gpioIrqRelease(void)
{
int32_t retVal;
struct tisci_msg_rm_irq_release_req rmIrqReq;
/* For releasing the IRQ for GPIO using sciclient APIs, we need to populate
* a structure, tisci_msg_rm_irq_release_req instantiated above. The definition
* of this struct and details regarding the struct members can be found in
* the tisci_rm_irq.h. These are similar to the struct members for the set request
* used above.
*/
/* Initialize all flags to zero since we'll be setting only a few */
rmIrqReq.valid_params = 0U;
/* Our request has a destination id, so enable the flag for DST ID */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
/* DST HOST IRQ is the output index of the interrupt router. We need to make sure this is also enabled as a valid param */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
/* This is not a global event */
rmIrqReq.global_event = 0U;
/* Our interrupt source would be the GPIO peripheral. The source id has to be a device id recognizable by the SYSFW.
* The list of device IDs can be found in tisci_devices.h file under source/drivers/sciclient/include/tisci/am64x_am243x/.
* In GPIO case there are 3 possible options - TISCI_DEV_GPIO0, TISCI_DEV_GPIO1, TISCI_DEV_MCU_GPIO0. For input interrupt,
* we need to choose the TISCI_DEV_GPIO1
*/
rmIrqReq.src_id = TISCI_DEV_GPIO1;
/* This is the interrupt source index within the GPIO peripheral */
rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 + GPIO_GET_BANK_INDEX(GPIO_PIN);
/* This is the destination of the interrupt, usually a CPU core. Here we choose the TISCI device ID for R5F0-0 core.
* For a different core, the corresponding TISCI device id has to be provided */
rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0;
/* This is the output index of the interrupt router. This depends on the core and board configuration */
rmIrqReq.dst_host_irq = Board_getGpioIntrNum();
/* Rest of the struct members are unused for GPIO interrupt */
rmIrqReq.ia_id = 0U;
rmIrqReq.vint = 0U;
rmIrqReq.vint_status_bit_index = 0U;
rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
/* To set the interrupt we now invoke the Sciclient_rmIrqRelease function which
* will find specifics about the route and request DMSC/SYSFW to relase/clear the interrupt
*/
retVal = Sciclient_rmIrqRelease(&rmIrqReq, SystemP_WAIT_FOREVER);
if(0 != retVal)
{
DebugP_log("[Error] Sciclient event reset failed!!!\r\n");
DebugP_assert(FALSE);
}
return;
}
