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Original question:

MCU-PLUS-SDK-AM243X: Using MCU_GPIO0_x in R5 gpio_input_interrupt example

MCU-PLUS-SDK-AM243X: Using MCU_GPIO0_x in R5 gpio_input_interrupt example

Bruno Bittner1
Intellectual 665 points
Part Number: MCU-PLUS-SDK-AM243X

This a continuation of the original issue, 1185701.

Summary: using mcu_plus_sdk_am64x_08_03_00_18,  modify examples/drivers/gpio/gpio_input_interrupt/ to use MCU_GPIO0_21 pin as interrupt source.  I'm using this version of SDK because later versions don't  have board.c.  I need board.c in order to setup to use MCU GPIO interrupt router, and I don't see how to do this using sysconfg.

I modified TISCI SYSFW to allow routing of MCU_GPIO0_x interrupts to R5FSS_0_0 core.  These interrupts would otherwise be routed to the M4 core. 

I see in board.c:Sciclient_rmIrqSet() that the interrupt route setup is sucessful.  I see that MCU_GPIO0_21 is toggling and I  can correctly read the state of the pin.  Interrupts should be happening, but they don't.

Can you provide a working example of interrupt code for R5 from MCU_GPIO0_x?  Can you check over the attached files?

2502.sciclient_defaultBoardcfg_rm.c
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/*
* K3 System Firmware Resource Management Configuration Data
* Auto generated from K3 Resource Partitioning tool
*
* Copyright (c) 2018-2020, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
1588.gpio_input_interrupt.c
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/*
* Copyright (C) 2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
2845.board.c
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/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0
    Intellectual 665 points

    I'm attempting to attach a syscfg file.  Changed to text file.

    example.syscfg.txt
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    /**
    * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
    * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
    * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM64x@08.03.00"
    * @versions {"tool":"1.14.0+2667"}
    */
    /**
    * Import the modules used in this configuration.
    */
    const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false);
    const gpio1 = gpio.addInstance();
    const gpio2 = gpio.addInstance();
    const debug_log = scripting.addModule("/kernel/dpl/debug_log");
    const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
    const mpu_armv71 = mpu_armv7.addInstance();
    const mpu_armv72 = mpu_armv7.addInstance();
    const mpu_armv73 = mpu_armv7.addInstance();
    const mpu_armv74 = mpu_armv7.addInstance();
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0
    Intellectual 665 points

    A possible place to cause an MCU_GPIO0_x interrupt on AM64-EVM is with MCU_UART1_RX_3V3 as MCU_GPIO0_14 at ball C9 that goes to Safety Connectror J1 pin 11.

  • 0 in reply to Bruno Bittner1
    Intellectual 665 points

    Here is a tar file of an example for AM64-EVM that shows the problem  I'm using MCU_UART1_CTS at pin10 of J1 on AM64-EVM.  untar at mcu_plus_sdk_am64x_08_03_00_18/examples/drivers/gpio

    Gives output:

    ...

    Interrupted 0 times(bank 1, val 1)
    Interrupted 0 times(bank 1, val 0)
    Interrupted 0 times(bank 1, val 0)
    Interrupted 0 times(bank 1, val 0)
    Interrupted 0 times(bank 1, val 1)
    Interrupted 0 times(bank 1, val 0)
    Interrupted 0 times(bank 1, val 1)
    Interrupted 0 times(bank 1, val 1)
    Interrupted 0 times(bank 1, val 1)
    Interrupted 0 times(bank 1, val 0)

    ...

    I used my TISCI SYSFW allowing MCU_GPIO interrupts routed to R5FSS0_0.  Using default SYSFW prints:

    Sciclient_rmIrqSet = -1
    [Error] Sciclient event config failed!!!
    ASSERT: 0.14369s: ../board.c:Sciclient_gpioIrqSet:122: FALSE failed !!!

    MCUGPIO.tar

  • 0 in reply to Bruno Bittner1
    TI__Mastermind 29198 points

    Hi Bruno,

    I'm not clear if you're planning on using the AM64x or the AM243x. I see you're using the AM64x SDK for your development, but your thread title & part number are for the AM243x. Which SOC are you using? I'm asking this so I can route your question to the correct support person.

    Regards,
    Frank

  • 0 in reply to Frank Livingston
    Intellectual 665 points

    HI Frank,

    This is for AM64x device.  

  • 0 in reply to Bruno Bittner1
    Intellectual 665 points

    I short J1 pin 10 to J1 pin 23 (GND) to attempt to generate an interrupt.  That's what changes the "val" in the above prints.

  • 0 in reply to Bruno Bittner1
    TI__Mastermind 33264 points

    Hi Bruno,

    I am going through the previous thread you have mentioned, here is the link just in case: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1185701/mcu-plus-sdk-am243x-using-mcu_gpio0_x-in-r5-gpio_input_interrupt-example

    Once I have gone through it I will probably get a background for this current thread.

    Please allow me some time to get back to you.

    Thanks,

    Vaibhav

  • 0 in reply to Bruno Bittner1
    TI__Mastermind 33264 points

    Hi Bruno,

    Correct me on my understanding of your query.

    You are trying to run the GPIO Input Interrupt Example for AM64x. If this is the case then the following FAQ(e2e.ti.com/.../faq-am64x-how-to-run-mcu-sdk-gpio_input_interrupt-example-for-r5fss0-0-with-linux-running-on-a53) will surely help you.

    Please have a look at it and let me know if it resolves your issue.

    Thanks,

    Vaibhav

  • 0 in reply to Vaibhav Kumar
    Intellectual 665 points

    Hi Vaibhav,

    I've done what it says the link:e2e.ti.com/.../faq-am64x-how-to-run-mcu-sdk-gpio_input_interrupt-example-for-r5fss0-0-with-linux-running-on-a53

    The difference between what I'm trying to do different from the supplied examples/drivers/gpio/gpio_input_interrupt example is use MCU domain MCU_GPIO0_x versus using MAIN domain GPIO1_x

    I've attached my sciclient_defaultBoardcfg_rm.c file above.  I'm only trying to make this work under MCU+ at this point.  I will work on linux after it is working under MCU+.

    I took the MCU_GPIO interrupt routers from the M4 core and moved them to the R5 core.  Please look at the attached MCUGPIO.tar file and compare to the standard example, this will show what I'm trying to do. 

  • 0 in reply to Bruno Bittner1
    Intellectual 665 points

    Here is a diff of the changes I made to sciclient_defaultBoardcfg_rm:

    $ diff -Naur sciclient_defaultBoardcfg_rm_ORIG.c sciclient_defaultBoardcfg_rm.c
    --- sciclient_defaultBoardcfg_rm_ORIG.c 2023-01-06 10:53:19.857596800 -0600
    +++ sciclient_defaultBoardcfg_rm.c 2023-03-16 10:24:59.221185500 -0500
    @@ -129,7 +129,7 @@
    .magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
    .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_resasg),
    },
    - .resasg_entries_size = 176 * sizeof(struct tisci_boardcfg_rm_resasg_entry),
    + .resasg_entries_size = 177 * sizeof(struct tisci_boardcfg_rm_resasg_entry),
    },
    },
    .resasg_entries = {
    @@ -212,16 +212,22 @@
    .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
    },
    {
    - .num_resource = 4,
    + .num_resource = 2,
    .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
    .start_resource = 0,
    - .host_id = TISCI_HOST_ID_A53_2,
    + .host_id = TISCI_HOST_ID_MAIN_0_R5_0, // this is like regular GPIO
    },
    {
    - .num_resource = 4,
    + .num_resource = 2,
    .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
    - .start_resource = 4,
    - .host_id = TISCI_HOST_ID_M4_0,
    + .start_resource = 0,
    + .host_id = TISCI_HOST_ID_MAIN_0_R5_1, // same as MAIN_0_R5_0?
    + },
    + {
    + .num_resource = 2,
    + .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
    + .start_resource = 2,
    + .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
    },
    {
    .num_resource = 41,

  • 0 in reply to Bruno Bittner1
    TI__Mastermind 33264 points

    Hi Bruno,

    I have looked a your query. Please allow me one to two days to get back to you.

    Regards,

    Vaibhav

  • 0 in reply to Vaibhav Kumar
    TI__Mastermind 39691 points

    Hello Bruno,

    SW5 is connected to MCU_GPIO and MAIN_GPIO.

    You can use same sw5 for MCU_GPIO interrupt test.

    Please update your code changes below.

    #define TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 (0U) - > use 30 for bank 0 interrupt and 31 for bank 1 interrupt.

    rmIrqReq.dst_host_irq = 0U; //0 to 3

    Prashant will share working code .

    Regards,

    S.Anil.

  • 0
    TI__Mastermind 39691 points
    Bruno Bittner1 said:
    Summary: using mcu_plus_sdk_am64x_08_03_00_18,  modify examples/drivers/gpio/gpio_input_interrupt/ to use MCU_GPIO0_21 pin as interrupt source.  I'm using this version of SDK because later versions don't  have board.c.  I need board.c in order to setup to use MCU GPIO interrupt router, and I don't see how to do this using sysconfg.

    Hello Bruno,

    You can use latest version MCU+SDK  .But you need to follow below steps .

    1. Configure GPIO pin as input in system config

    2. Add the board.c file to your workspace and edit the changes

    3. Build

    Regards,

    S.ANil.

  • 0 in reply to Swargam Anil
    TI__Guru 57651 points

    Hello Bruno,

    RM Board Configuration

    Your RM Board configurations are right only.

    Bruno Bittner1 said:
    + .host_id = TISCI_HOST_ID_MAIN_0_R5_1, // same as MAIN_0_R5_0?

    About this, TISCI_HOST_ID_MAIN_0_R5_1 is the non-secure context id for R5FSS0-0 core. It is required because GPIO interrupt routing is set via non-secure TISCI message type.

    Working example code

    Following Anil's suggestion, below is the working code's patch to be applied on the original gpio_input_interrupt example in MCU+ SDK v8.3

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    diff --git a/examples/drivers/gpio/gpio_input_interrupt/am64x-evm/r5fss0-0_nortos/board.c b/examples/drivers/gpio/gpio_input_interrupt/am64x-evm/r5fss0-0_nortos/board.c
    index c7a7bb4..e6ba263 100644
    --- a/examples/drivers/gpio/gpio_input_interrupt/am64x-evm/r5fss0-0_nortos/board.c
    +++ b/examples/drivers/gpio/gpio_input_interrupt/am64x-evm/r5fss0-0_nortos/board.c
    @@ -40,13 +40,13 @@
    * Board info
    */
    /* This is based on DMSC board config and core */
    -#define BOARD_BUTTON_GPIO_INTR_NUM (CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_8)
    +#define BOARD_BUTTON_GPIO_INTR_NUM (CSLR_R5FSS0_CORE0_INTR_MCU_MCU_GPIOMUX_INTROUTER0_OUTP_0)
    #define BOARD_BUTTON_GPIO_SWITCH_NUM (5)
    /** \brief bank interrupt source index base */
    #define TISCI_BANK_SRC_IDX_BASE_GPIO0 (90U)
    #define TISCI_BANK_SRC_IDX_BASE_GPIO1 (90U)
    -#define TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 (90U)
    +#define TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 (30U)
    static void Sciclient_gpioIrqSet(void);
    static void Sciclient_gpioIrqRelease(void);
    @@ -95,9 +95,9 @@ static void Sciclient_gpioIrqSet(void)
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    For convenience, attached below is the working example code as a ZIP file.

    gpio_input_interrupt.zip

    Regards,

    Prashant

  • 0 in reply to Prashant Shivhare
    Intellectual 665 points

    I will try this out and get back to you in a day or two.

  • +1 in reply to Bruno Bittner1
    TI__Guru 57651 points

    Sure, Bruno. Let us know at your convenience.

  • 0 in reply to Prashant Shivhare
    Intellectual 665 points

    It works!  But I don't understand setting  TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 to 30.  I understand  TISCI_BANK_SRC_IDX_BASE_GPIO1 being 90.  What would the proper setting be for  TISCI_BANK_SRC_IDX_BASE_GPIO0?

  • 0 in reply to Bruno Bittner1
    TI__Guru 57651 points

    Hi Bruno,

    The value is set to 30 due to the fact that Bank 0 interrupt is connected to input pin no. 30th of MCU GPIO Interrupt Router.

    Regards,

    Prashant

  • 0 in reply to Prashant Shivhare
    Intellectual 665 points

    Hi Prashant, thanks for the response!

    One more thing: how would one change the example to use  a pin interrupt instead of a bank interrupt?

    To me the original example seems to be doing a bank interrupt, then masking to emulate a bit interrupt.

  • 0 in reply to Bruno Bittner1
    TI__Mastermind 39691 points
    Bruno Bittner1 said:

    One more thing: how would one change the example to use  a pin interrupt instead of a bank interrupt?

    Hello Bruno,

    You can try the steps below and let us know if you face any issues.

    1. Change rmIrqReq.src_index value to PIN number instead of bank value = PIN_NO;
    2. Remove or comment out the line below
    GPIO_bankIntrEnable(gGpioBaseAddr, bankNum);

    3.Use below two functions instead of Bank functions in ISR routine 

    GPIO_getIntrStatus

    GPIO_clearIntrStatus

    Regards,

    S.Anil.

  • 0 in reply to Swargam Anil
    TI__Mastermind 39691 points

    Hello Bruno,

    You can use first step instead of giving bank number, you can give pin number .

    So, you can get interrupt on pin and not from bank interrupt . I checked on my side and it is working .

    Regards,

    S.Anil.

  • 0 in reply to Swargam Anil
    Intellectual 665 points

    Thanks S.Anil, Can you provide the code for the MCU_GPIO pin interrupt, because I thought that was what I was doing.

  • +1 in reply to Bruno Bittner1
    TI__Guru 57651 points

    Hi Bruno,

    Below is the required patch for pin interrupt configuration

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    diff --git a/examples/drivers/gpio/gpio_input_interrupt/am64x-evm/r5fss0-0_nortos/board.c b/examples/drivers/gpio/gpio_input_interrupt/am64x-evm/r5fss0-0_nortos/board.c
    index e6ba263..d852780 100644
    --- a/examples/drivers/gpio/gpio_input_interrupt/am64x-evm/r5fss0-0_nortos/board.c
    +++ b/examples/drivers/gpio/gpio_input_interrupt/am64x-evm/r5fss0-0_nortos/board.c
    @@ -47,6 +47,7 @@
    #define TISCI_BANK_SRC_IDX_BASE_GPIO0 (90U)
    #define TISCI_BANK_SRC_IDX_BASE_GPIO1 (90U)
    #define TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 (30U)
    +#define TISCI_PIN_SRC_IDX_BASE_MCU_GPIO0 (0U)
    static void Sciclient_gpioIrqSet(void);
    static void Sciclient_gpioIrqRelease(void);
    @@ -97,7 +98,7 @@ static void Sciclient_gpioIrqSet(void)
    */
    rmIrqReq.src_id = TISCI_DEV_MCU_GPIO0;
    /* This is the interrupt source index within the GPIO peripheral */
    - rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0 + GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN);
    + rmIrqReq.src_index = TISCI_PIN_SRC_IDX_BASE_MCU_GPIO0 + GPIO_PUSH_BUTTON_PIN;
    /* This is the destination of the interrupt, usually a CPU core. Here we choose the TISCI device ID for R5F0-0 core.
    * For a different core, the corresponding TISCI device id has to be provided */
    rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0;
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Regards,

    Prashant