AM2634: FOut != 0 failed

Hi Andrei Zinenko,

Can you share more information on this...

1. Which examples are you trying ?

2. What is your boot mode setting ?

3. Are you using the GEL scripts to initialize your system ?

4. Can you try with SBL NULL and without loading the GEL Scripts ?

Best Regards,
Aakash

Hi,

Please follow the following cheat-sheet for the boot combination understanding -

Anything outside this is very custom and might not be supported in SDK by default.

Best Regards,
Aakash

Dear Aakash Kedia,

Thank you for fast response. Regarding your questions, here the information:

1. I tried the several projects:

     - adc_soc_continuous_am263x-cc_r5fss0-0_nortos_ti-arm-clang

    - gpio_multi_led_blink_am263x-cc_r5fss0-0_nortos_ti-arm-clang

2. I use QSPI BOOT MODE in AM263X-CC evaluation board

3. I use the project as is and I can conclude it uses the GEL scripts from this:

Cortex_R5_0: GEL Output: Loading Gel Files on R5F0
Cortex_R5_0: GEL Output: Gel files loading on R5F0 Complete
Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***

Cortex_R5_0: GEL Output: AM263x Initialization Scripts Launched.
Please Wait...

Cortex_R5_0: GEL Output: AM263x_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present
Cortex_R5_0: GEL Output: AM263x_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x00000004
Cortex_R5_0: GEL Output:
QSPI - 4S Fallback UART boot mode
Cortex_R5_0: GEL Output: AM263x_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
Cortex_R5_0: GEL Output: AM263x_Check_supported_mode() Launched
Cortex_R5_0: GEL Output:
efuse1=0x01000000
Cortex_R5_0: GEL Output:
The Device supports both LockStep & Dual Core mode
Cortex_R5_0: GEL Output:
mode = 0
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output:

***R5FSS0 Reset for Lockstep ***
Cortex_R5_0: GEL Output:

*** R5FSS1 Reset for Lockstep ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output:

All R5F Cores Released for program load
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: *********** R5FSS0/1 Lockstep mode Configured********
Cortex_R5_0: GEL Output: PER PLL Configuration Complete
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output:
CLK Programmed R5F=400MHz and SYS_CLK=200MHz
Cortex_R5_0: GEL Output:

*** Enabling Peripheral Clocks ***
Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
Cortex_R5_0: GEL Output: Enabling QSPI Clocks
Cortex_R5_0: GEL Output: Enabling I2C Clocks
Cortex_R5_0: GEL Output: Enabling TRACE Clocks
Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks
Cortex_R5_0: GEL Output: Enabling GPMC Clocks
Cortex_R5_0: GEL Output: Enabling ELM Clocks
Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
Cortex_R5_0: GEL Output: Enabling CPTS Clocks
Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
Cortex_R5_0: GEL Output:

***All IP Clocks are Enabled***

Cortex_R5_0: GEL Output: CPU reset (soft reset) has been issued through GEL.

4. Please guide me how to do  SBL NULL and without loading the GEL Scripts

Kind regards,

Andrei

More information.

That is what I found after some debugging

in file soc_rom.c in functionn SOC_rcmGetCoreFout()

When it NOT works:

ptrTopRCMRegs->PLL_CORE_M2NDIV =  65547

causing N = 11

ptrTopRCMRegs->PLL_CORE_MN2DIV = 65920

causing M = 384

Then with this parameters it cannot match any entry in table 

const SOC_RcmADPLLJConfig_t gADPLLJConfigTbl[] =
{
/* CORE_2000_25MHz */
{
    .Finp = 25U,
    .N = 9U,
    .Fout = 2000U,
    .M2 = 1U,
    .M = 800U,
   .FracM = 0U,
},
/* PER_1920_25MHz */
{
    .Finp = 25U,
    .N = 9U,
    .Fout = 1920U,
    .M2 = 1U,
    .M = 768U,
    .FracM = 0U,
},
};

causing function SOC_rcmADPLLJGetFOut() return FOut = 0

doing the assert with printout

[Cortex_R5_0] ASSERT: 0.3s: soc/am263x/soc_rcm.c:SOC_rcmGetCoreFout:1521: FOut != 0 failed !!!

From time to time it DO works. Then:

ptrTopRCMRegs->PLL_CORE_M2NDIV =  65545

causing N = 9

ptrTopRCMRegs->PLL_CORE_MN2DIV = 768

causing M = 768

causing function SOC_rcmADPLLJGetFOut() return Fout = 1920*1000 *1000

May be this can give you some direction

Andrei

More information.

That is what I found after some debugging

in file soc_rom.c in functionn SOC_rcmGetCoreFout()

When it NOT works:

ptrTopRCMRegs->PLL_CORE_M2NDIV =  65547

causing N = 11

ptrTopRCMRegs->PLL_CORE_MN2DIV = 65920

causing M = 384

Then with this parameters it cannot match any entry in table 

const SOC_RcmADPLLJConfig_t gADPLLJConfigTbl[] =
{
/* CORE_2000_25MHz */
{
    .Finp = 25U,
    .N = 9U,
    .Fout = 2000U,
    .M2 = 1U,
    .M = 800U,
   .FracM = 0U,
},
/* PER_1920_25MHz */
{
    .Finp = 25U,
    .N = 9U,
    .Fout = 1920U,
    .M2 = 1U,
    .M = 768U,
    .FracM = 0U,
},
};

causing function SOC_rcmADPLLJGetFOut() return FOut = 0

doing the assert with printout

[Cortex_R5_0] ASSERT: 0.3s: soc/am263x/soc_rcm.c:SOC_rcmGetCoreFout:1521: FOut != 0 failed !!!

From time to time it DO works. Then:

ptrTopRCMRegs->PLL_CORE_M2NDIV =  65545

causing N = 9

ptrTopRCMRegs->PLL_CORE_MN2DIV = 768

causing M = 768

causing function SOC_rcmADPLLJGetFOut() return Fout = 1920*1000 *1000

May be this can give you some direction

Andrei

Do you have any idea why 

ptrTopRCMRegs->PLL_CORE_M2NDIV =  65547 instead of 65545

and

ptrTopRCMRegs->PLL_CORE_MN2DIV = 65920 instead of 768

???

Andrei