TM4C1290NCPDT: About SPI Read

user5850039

Prodigy 215 points

Part Number: TM4C1290NCPDT

Hi,

We are using TM4C1290NCPDTI3R for our system host.

We found "stair step" on SPI clock edge.

So,we are worried about miss latch of read data.

Therefore I have a question. Please refer to attached file.

I think that if TM4C1290NCPDTI3R is Type2 described in the attached file, miss latch doesn't happen.

How about you?

Thank you

TM4C1290NCPDTI3R.pptx

over 2 years ago

0 Charles Tsai over 2 years ago

TI__Guru**** 191886 points

Hi,

It will be the type 2 implementation where the master uses internal clock to sample the data.

Additional information, for slave operation where you are receiving SPI clock from the external master, there is a minimum of 0.49V of hysteresis on the I/Os.

0 user5850039 over 2 years ago

Prodigy 215 points

Hi,

Thank you for your reply.

I understood that TM4C1290NCPDTI3R has Type2 implementation and "stair step" on clock edge is no problem for SPI read.

Thank you

Arm-based microcontrollers

Arm-based microcontrollers forum

TM4C1290NCPDT: About SPI Read