EK-TM4C123GXL: EK-TM4C123GXL during send SPI data than have on Analog input rms -30db noise

Kevin Hinrichs

Prodigy 180 points

Part Number: EK-TM4C123GXL

I need to use all 4 SPI data connections.

When the data is sending over SPI, than the noise during sampling a analog input is very much increasing to rms -30db.

Is that a common issue ?

over 2 years ago

0 Charles Tsai over 2 years ago

TI__Guru**** 184346 points

Hi,

I'm not clear as what you are trying to do. Are you saying you are using a SPI with 4 pins while you use the ADC to sample an analog input? Noise got coupled into the ADC input when SPI pins are running?

0 Kevin Hinrichs over 2 years ago in reply to Charles Tsai

Prodigy 180 points

I use 4 SPI GPIO pins to send data.
I have configured them as follows:

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#define SSI_CLOCK (4800000)
void init_SSI0()
{
    // enable SSI1 Tx PA5 only
    
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_SSI0));
    
    // port config
    MAP_GPIOPinConfigure(GPIO_PA5_SSI0TX);
    MAP_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5);
    
    MAP_GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, 
                         GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD);
    
    // SSI config
    MAP_IntDisable(INT_SSI0);
    MAP_SSIIntDisable(SSI0_BASE, SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR);
    MAP_SSIDisable(SSI0_BASE);
    MAP_SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_1, 
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#define SSI_CLOCK (4800000)

void init_SSI0()
{
    // enable SSI1 Tx PA5 only
    
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_SSI0));
    
    // port config
    MAP_GPIOPinConfigure(GPIO_PA5_SSI0TX);
    MAP_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5);
    
    MAP_GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, 
                         GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD);
    
    // SSI config
    MAP_IntDisable(INT_SSI0);
    MAP_SSIIntDisable(SSI0_BASE, SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR);
    MAP_SSIDisable(SSI0_BASE);
    MAP_SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_1, 
                           SSI_MODE_MASTER, SSI_CLOCK, 8);
    
    // ------------------ //
    // Priority Levels
    // Priority 4 = 0xE0 ->lower
    // Priority 3 = 0x60
    // Priority 2 = 0x20
    // Priority 1 = 0x00 ->higher
    // ------------------ //
    
    MAP_IntPrioritySet(INT_SSI0, 0x00); // Priority 1 !!!
    MAP_IntEnable(INT_SSI0);
    MAP_SSIEnable(SSI0_BASE);
}

void init_SSI1()
{
    // enable SSI1 Tx PF1 only
    
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_SSI1));
    
    // port config
    MAP_GPIOPinConfigure(GPIO_PF1_SSI1TX);
    MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_1);
    
    MAP_GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_1, 
                         GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD);
    
    // SSI config
    MAP_IntDisable(INT_SSI1);
    MAP_SSIIntDisable(SSI1_BASE, SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR);
    MAP_SSIDisable(SSI1_BASE);
    
    MAP_SSIConfigSetExpClk(SSI1_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_1, 
                           SSI_MODE_MASTER, SSI_CLOCK, 8);
    
    // ------------------ //
    // Priority Levels
    // Priority 4 = 0xE0 ->lower
    // Priority 3 = 0x60
    // Priority 2 = 0x20
    // Priority 1 = 0x00 ->higher
    // ------------------ //
    
    MAP_IntPrioritySet(INT_SSI1, 0x00); // Priority 1 !!!
    MAP_IntEnable(INT_SSI1);
    MAP_SSIEnable(SSI1_BASE);
}

void init_SSI2()
{
    // enable SSI2 Tx PB7 only
    
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_SSI2));
    
    // port config
    MAP_GPIOPinConfigure(GPIO_PB7_SSI2TX);
    MAP_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_7);
    
    MAP_GPIOPadConfigSet(GPIO_PORTB_BASE, GPIO_PIN_7, 
                         GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD);
    
    // SSI config
    MAP_IntDisable(INT_SSI2);
    MAP_SSIIntDisable(SSI2_BASE, SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR);
    MAP_SSIDisable(SSI2_BASE);
    
    MAP_SSIConfigSetExpClk(SSI2_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_1, 
                           SSI_MODE_MASTER, SSI_CLOCK, 8);
    
    // ------------------ //
    // Priority Levels
    // Priority 4 = 0xE0 ->lower
    // Priority 3 = 0x60
    // Priority 2 = 0x20
    // Priority 1 = 0x00 ->higher
    // ------------------ //
    
    MAP_IntPrioritySet(INT_SSI2, 0x00); // Priority 1 !!!
    MAP_IntEnable(INT_SSI2);
    MAP_SSIEnable(SSI2_BASE);
}

void init_SSI3()
{
    // enable SSI3 Tx PD3 only
    
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_SSI3));
    
    // port config
    MAP_GPIOPinConfigure(GPIO_PD3_SSI3TX);
    MAP_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_3);
    
    MAP_GPIOPadConfigSet(GPIO_PORTD_BASE, GPIO_PIN_3, 
                         GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD);
    
    // SSI config
    MAP_IntDisable(INT_SSI3);
    MAP_SSIIntDisable(SSI3_BASE, SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR);
    MAP_SSIDisable(SSI3_BASE);
    
    MAP_SSIConfigSetExpClk(SSI3_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_1, 
                           SSI_MODE_MASTER, SSI_CLOCK, 8);
    
    // ------------------ //
    // Priority Levels
    // Priority 4 = 0xE0 ->lower
    // Priority 3 = 0x60
    // Priority 2 = 0x20
    // Priority 1 = 0x00 ->higher
    // ------------------ //
    
    MAP_IntPrioritySet(INT_SSI3, 0x00); // Priority 1 !!!
    MAP_IntEnable(INT_SSI3);
    MAP_SSIEnable(SSI3_BASE);
}

I the uDMA part:

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void init_uDMA_SSI0()
{
    // signal 0
    // uDMA Channel 11
    MAP_SSIDMADisable(SSI0_BASE, SSI_DMA_RX | SSI_DMA_TX);
    
    MAP_uDMAChannelAssign(UDMA_CH11_SSI0TX);
    MAP_uDMAChannelAttributeDisable(11, 
                                    UDMA_ATTR_ALTSELECT | 
                                    UDMA_ATTR_HIGH_PRIORITY | 
                                    UDMA_ATTR_REQMASK | 
                                    UDMA_ATTR_USEBURST);
    
    MAP_uDMAChannelControlSet(11 | UDMA_PRI_SELECT, 
                              UDMA_SIZE_8 | UDMA_SRC_INC_8 | 
                              UDMA_DST_INC_NONE | UDMA_ARB_4);
    
    MAP_uDMAChannelControlSet(11 | UDMA_ALT_SELECT, 
                              UDMA_SIZE_8 | UDMA_SRC_INC_8 | 
                              UDMA_DST_INC_NONE | UDMA_ARB_4);
    
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void init_uDMA_SSI0()
{
    // signal 0
    // uDMA Channel 11
    MAP_SSIDMADisable(SSI0_BASE, SSI_DMA_RX | SSI_DMA_TX);
    
    MAP_uDMAChannelAssign(UDMA_CH11_SSI0TX);
    MAP_uDMAChannelAttributeDisable(11, 
                                    UDMA_ATTR_ALTSELECT | 
                                    UDMA_ATTR_HIGH_PRIORITY | 
                                    UDMA_ATTR_REQMASK | 
                                    UDMA_ATTR_USEBURST);
    
    MAP_uDMAChannelControlSet(11 | UDMA_PRI_SELECT, 
                              UDMA_SIZE_8 | UDMA_SRC_INC_8 | 
                              UDMA_DST_INC_NONE | UDMA_ARB_4);
    
    MAP_uDMAChannelControlSet(11 | UDMA_ALT_SELECT, 
                              UDMA_SIZE_8 | UDMA_SRC_INC_8 | 
                              UDMA_DST_INC_NONE | UDMA_ARB_4);
    
    //MAP_uDMAChannelAttributeEnable(11, UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY);
    MAP_SSIDMAEnable(SSI0_BASE, SSI_DMA_TX);
    MAP_SSIEnable(SSI0_BASE);
}

void init_uDMA_SSI1()
{
    // signal 1
    // uDMA Channel 25
    MAP_SSIDMADisable(SSI1_BASE, SSI_DMA_RX | SSI_DMA_TX);
    
    MAP_uDMAChannelAssign(UDMA_CH25_SSI1TX);
    MAP_uDMAChannelAttributeDisable(25, 
                                    UDMA_ATTR_ALTSELECT | 
                                    UDMA_ATTR_HIGH_PRIORITY | 
                                    UDMA_ATTR_REQMASK | 
                                    UDMA_ATTR_USEBURST);
    
    MAP_uDMAChannelControlSet(25 | UDMA_PRI_SELECT, 
                              UDMA_SIZE_8 | UDMA_SRC_INC_8 | 
                              UDMA_DST_INC_NONE | UDMA_ARB_4);
    
    MAP_uDMAChannelControlSet(25 | UDMA_ALT_SELECT, 
                              UDMA_SIZE_8 | UDMA_SRC_INC_8 | 
                              UDMA_DST_INC_NONE | UDMA_ARB_4);
    
    //MAP_uDMAChannelAttributeEnable(25, UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY);
    MAP_SSIDMAEnable(SSI1_BASE, SSI_DMA_TX);
    MAP_SSIEnable(SSI1_BASE);
}

void init_uDMA_SSI2()
{
    // signal 2
    // uDMA Channel 13
    MAP_SSIDMADisable(SSI2_BASE, SSI_DMA_RX | SSI_DMA_TX);
    
    MAP_uDMAChannelAssign(UDMA_CH13_SSI2TX);
    MAP_uDMAChannelAttributeDisable(13, 
                                    UDMA_ATTR_ALTSELECT | 
                                    UDMA_ATTR_HIGH_PRIORITY | 
                                    UDMA_ATTR_REQMASK | 
                                    UDMA_ATTR_USEBURST);
    
    MAP_uDMAChannelControlSet(13 | UDMA_PRI_SELECT, 
                              UDMA_SIZE_8 | UDMA_SRC_INC_8 | 
                              UDMA_DST_INC_NONE | UDMA_ARB_4);
    
    MAP_uDMAChannelControlSet(13 | UDMA_ALT_SELECT, 
                              UDMA_SIZE_8 | UDMA_SRC_INC_8 | 
                              UDMA_DST_INC_NONE | UDMA_ARB_4);
    
    //MAP_uDMAChannelAttributeEnable(13, UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY);
    MAP_SSIDMAEnable(SSI2_BASE, SSI_DMA_TX);
    MAP_SSIEnable(SSI2_BASE);
}

void init_uDMA_SSI3()
{
    // signal 3
    // uDMA Channel 15
    MAP_SSIDMADisable(SSI3_BASE, SSI_DMA_RX | SSI_DMA_TX);
    
    MAP_uDMAChannelAssign(UDMA_CH15_SSI3TX);
    MAP_uDMAChannelAttributeDisable(15, 
                                    UDMA_ATTR_ALTSELECT | 
                                    UDMA_ATTR_HIGH_PRIORITY | 
                                    UDMA_ATTR_REQMASK | 
                                    UDMA_ATTR_USEBURST);
    
    MAP_uDMAChannelControlSet(15 | UDMA_PRI_SELECT, 
                              UDMA_SIZE_8 | UDMA_SRC_INC_8 | 
                              UDMA_DST_INC_NONE | UDMA_ARB_4);
    
    MAP_uDMAChannelControlSet(15 | UDMA_ALT_SELECT, 
                              UDMA_SIZE_8 | UDMA_SRC_INC_8 | 
                              UDMA_DST_INC_NONE | UDMA_ARB_4);
    
    //MAP_uDMAChannelAttributeEnable(15, UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY);
    MAP_SSIDMAEnable(SSI3_BASE, SSI_DMA_TX);
    MAP_SSIEnable(SSI3_BASE);
}

i send the data with uDMA over SPI. the data is prepared in the sram.

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void start_uDMA_SSI0()
{
    MAP_uDMAChannelTransferSet(11 | UDMA_PRI_SELECT, 
                               UDMA_MODE_PINGPONG, &uDMABufferSSI0_PRI, 
                               (void *)(SSI0_BASE + SSI_O_DR), 
                               SSI_TRANSFERSIZE);
    
    MAP_uDMAChannelEnable(11 | UDMA_PRI_SELECT);
    uDMABufferStateSSI0_PRI = EMPTYING;
    uDMABufferModeSSI0 = PING;
    
    MAP_uDMAChannelTransferSet(11 | UDMA_ALT_SELECT, 
                               UDMA_MODE_PINGPONG, &uDMABufferSSI0_ALT, 
                               (void *)(SSI0_BASE + SSI_O_DR), 
                               SSI_TRANSFERSIZE);
    
    MAP_uDMAChannelEnable(11 | UDMA_ALT_SELECT);
    uDMABufferStateSSI0_ALT = EMPTYING;
    uDMABufferModeSSI0 = PONG;
}
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void start_uDMA_SSI0()
{
    MAP_uDMAChannelTransferSet(11 | UDMA_PRI_SELECT, 
                               UDMA_MODE_PINGPONG, &uDMABufferSSI0_PRI, 
                               (void *)(SSI0_BASE + SSI_O_DR), 
                               SSI_TRANSFERSIZE);
    
    MAP_uDMAChannelEnable(11 | UDMA_PRI_SELECT);
    uDMABufferStateSSI0_PRI = EMPTYING;
    uDMABufferModeSSI0 = PING;
    
    MAP_uDMAChannelTransferSet(11 | UDMA_ALT_SELECT, 
                               UDMA_MODE_PINGPONG, &uDMABufferSSI0_ALT, 
                               (void *)(SSI0_BASE + SSI_O_DR), 
                               SSI_TRANSFERSIZE);
    
    MAP_uDMAChannelEnable(11 | UDMA_ALT_SELECT);
    uDMABufferStateSSI0_ALT = EMPTYING;
    uDMABufferModeSSI0 = PONG;
}

void start_uDMA_SSI1()
{
    MAP_uDMAChannelTransferSet(25 | UDMA_PRI_SELECT, 
                               UDMA_MODE_PINGPONG, &uDMABufferSSI1_PRI, 
                               (void *)(SSI1_BASE + SSI_O_DR), 
                               SSI_TRANSFERSIZE);
    
    MAP_uDMAChannelEnable(25 | UDMA_PRI_SELECT);
    uDMABufferStateSSI1_PRI = EMPTYING;
    uDMABufferModeSSI1 = PING;
    
    MAP_uDMAChannelTransferSet(25 | UDMA_ALT_SELECT, 
                               UDMA_MODE_PINGPONG, &uDMABufferSSI1_ALT, 
                               (void *)(SSI1_BASE + SSI_O_DR), 
                               SSI_TRANSFERSIZE);
    
    MAP_uDMAChannelEnable(25 | UDMA_ALT_SELECT);
    uDMABufferStateSSI1_ALT = EMPTYING;
    uDMABufferModeSSI1 = PONG;
}

void start_uDMA_SSI2()
{
    MAP_uDMAChannelTransferSet(13 | UDMA_PRI_SELECT, 
                               UDMA_MODE_PINGPONG, &uDMABufferSSI2_PRI, 
                               (void *)(SSI2_BASE + SSI_O_DR), 
                               SSI_TRANSFERSIZE);
    
    MAP_uDMAChannelEnable(13 | UDMA_PRI_SELECT);
    uDMABufferStateSSI2_PRI = EMPTYING;
    uDMABufferModeSSI2 = PING;
    
    MAP_uDMAChannelTransferSet(13 | UDMA_ALT_SELECT, 
                               UDMA_MODE_PINGPONG, &uDMABufferSSI2_ALT, 
                               (void *)(SSI2_BASE + SSI_O_DR), 
                               SSI_TRANSFERSIZE);
    
    MAP_uDMAChannelEnable(13 | UDMA_ALT_SELECT);
    uDMABufferStateSSI2_ALT = EMPTYING;
    uDMABufferModeSSI2 = PONG;
}

void start_uDMA_SSI3()
{
    MAP_uDMAChannelTransferSet(15 | UDMA_PRI_SELECT, 
                               UDMA_MODE_PINGPONG, &uDMABufferSSI3_PRI, 
                               (void *)(SSI3_BASE + SSI_O_DR), 
                               SSI_TRANSFERSIZE);
    
    MAP_uDMAChannelEnable(15 | UDMA_PRI_SELECT);
    uDMABufferStateSSI3_PRI = EMPTYING;
    uDMABufferModeSSI3 = PING;
    
    MAP_uDMAChannelTransferSet(15 | UDMA_ALT_SELECT, 
                               UDMA_MODE_PINGPONG, &uDMABufferSSI3_ALT, 
                               (void *)(SSI3_BASE + SSI_O_DR), 
                               SSI_TRANSFERSIZE);
    
    MAP_uDMAChannelEnable(15 | UDMA_ALT_SELECT);
    uDMABufferStateSSI3_ALT = EMPTYING;
    uDMABufferModeSSI3 = PING;
}

then i start the 4 SPI streams together:

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void startDMABufferSSI()
{
    start_uDMA_SSI0();
    MAP_SysCtlDelay(70);
    
    start_uDMA_SSI1();
    MAP_SysCtlDelay(70);
    
    start_uDMA_SSI2();
    MAP_SysCtlDelay(70);
    
    start_uDMA_SSI3();
    
    resetCode = 1;
}
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void startDMABufferSSI()
{
    start_uDMA_SSI0();
    MAP_SysCtlDelay(70);
    
    start_uDMA_SSI1();
    MAP_SysCtlDelay(70);
    
    start_uDMA_SSI2();
    MAP_SysCtlDelay(70);
    
    start_uDMA_SSI3();
    
    resetCode = 1;
}

The small delay is imported because it could be that ss1 stops before the sending is finished.

I don't know why, but that's another problem.

when the data sending is finished than the new data will be prepared and the the sending starts again in a loop.

here are the Interrupts Handlers

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void uDMASSI0IntHandler(void)
{
    MAP_SSIIntClear(SSI0_BASE, SSI_RXTO | SSI_RXOR); // Do I have to do that?
    MAP_uDMAIntClear(11); // Do I have to do that?
    
    if (MAP_uDMAChannelModeGet(11 | UDMA_PRI_SELECT) == UDMA_MODE_STOP)
    {
        uDMABufferStateSSI0_PRI = EMPTY;
    }
    
    if (MAP_uDMAChannelModeGet(11 | UDMA_ALT_SELECT) == UDMA_MODE_STOP)
    {
        uDMABufferStateSSI0_ALT = EMPTY;
    }
}
void uDMASSI1IntHandler(void)
{
    MAP_SSIIntClear(SSI1_BASE, SSI_RXTO | SSI_RXOR); // Do I have to do that?
    MAP_uDMAIntClear(25); // Do I have to do that?
    
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void uDMASSI0IntHandler(void)
{
    MAP_SSIIntClear(SSI0_BASE, SSI_RXTO | SSI_RXOR); // Do I have to do that?
    MAP_uDMAIntClear(11); // Do I have to do that?
    
    if (MAP_uDMAChannelModeGet(11 | UDMA_PRI_SELECT) == UDMA_MODE_STOP)
    {
        uDMABufferStateSSI0_PRI = EMPTY;
    }
    
    if (MAP_uDMAChannelModeGet(11 | UDMA_ALT_SELECT) == UDMA_MODE_STOP)
    {
        uDMABufferStateSSI0_ALT = EMPTY;
    }
}

void uDMASSI1IntHandler(void)
{
    MAP_SSIIntClear(SSI1_BASE, SSI_RXTO | SSI_RXOR); // Do I have to do that?
    MAP_uDMAIntClear(25); // Do I have to do that?
    
    if (MAP_uDMAChannelModeGet(25 | UDMA_PRI_SELECT) == UDMA_MODE_STOP)
    {
        uDMABufferStateSSI1_PRI = EMPTY;
    }
    
    if (MAP_uDMAChannelModeGet(25 | UDMA_ALT_SELECT) == UDMA_MODE_STOP)
    {
        uDMABufferStateSSI1_ALT = EMPTY;
    }
}

void uDMASSI2IntHandler(void)
{
    MAP_SSIIntClear(SSI2_BASE, SSI_RXTO | SSI_RXOR); // Do I have to do that?
    MAP_uDMAIntClear(13); // Do I have to do that?
    
    if (MAP_uDMAChannelModeGet(13 | UDMA_PRI_SELECT) == UDMA_MODE_STOP)
    {
        uDMABufferStateSSI2_PRI = EMPTY;
    }
    
    if (MAP_uDMAChannelModeGet(13 | UDMA_ALT_SELECT) == UDMA_MODE_STOP)
    {
        uDMABufferStateSSI2_ALT = EMPTY;
    }
}

void uDMASSI3IntHandler(void)
{
    MAP_SSIIntClear(SSI3_BASE, SSI_RXTO | SSI_RXOR); // Do I have to do that?
    MAP_uDMAIntClear(15); // Do I have to do that?
    
    if (MAP_uDMAChannelModeGet(15 | UDMA_PRI_SELECT) == UDMA_MODE_STOP)
    {
        uDMABufferStateSSI3_PRI = EMPTY;
    }
    
    if (MAP_uDMAChannelModeGet(15 | UDMA_ALT_SELECT) == UDMA_MODE_STOP)
    {
        uDMABufferStateSSI3_ALT = EMPTY;
        
        // enable timer for reset code
        MAP_TimerEnable(WTIMER5_BASE, TIMER_B);
    }
}

parallel to sending the data via SPI, an analog input is also recorded.

the trigger comes from a timer

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#define ADC_SAMPLING_RATE (44100)
void init_TIMER_2()
{
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER2);
    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_TIMER2));
    
    // Timer 2A is PB0 trigger for ADC0 SS3
    // Timer 2B is PB1 not used
    
    MAP_TimerConfigure(TIMER2_BASE, TIMER_CFG_SPLIT_PAIR | 
                       TIMER_CFG_A_PERIODIC | TIMER_CFG_B_ONE_SHOT);
    
    // Timer 2A
    // set ADC0 SS3 sampling rate
    MAP_TimerLoadSet(TIMER2_BASE, TIMER_A,
                     (SysCtlClockGet()/ADC_SAMPLING_RATE) - 1);
    
    // Timer 2A
    // enable the ADC trigger output for Timer A.
    MAP_TimerControlTrigger(TIMER2_BASE, TIMER_A, true);
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#define ADC_SAMPLING_RATE (44100)

void init_TIMER_2()
{
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER2);
    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_TIMER2));
    
    // Timer 2A is PB0 trigger for ADC0 SS3
    // Timer 2B is PB1 not used
    
    MAP_TimerConfigure(TIMER2_BASE, TIMER_CFG_SPLIT_PAIR | 
                       TIMER_CFG_A_PERIODIC | TIMER_CFG_B_ONE_SHOT);
    
    // Timer 2A
    // set ADC0 SS3 sampling rate
    MAP_TimerLoadSet(TIMER2_BASE, TIMER_A,
                     (SysCtlClockGet()/ADC_SAMPLING_RATE) - 1);
    
    // Timer 2A
    // enable the ADC trigger output for Timer A.
    MAP_TimerControlTrigger(TIMER2_BASE, TIMER_A, true);
    
    // Timer 2A
    // enable timer done interrupt
    MAP_TimerIntEnable(TIMER2_BASE, TIMER_TIMA_TIMEOUT);
}

recording with uDMA

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void init_uDMA_MIC0()
{
    // adc mic setup
    // uDMA Channel 17
    MAP_uDMAChannelAssign(UDMA_CH17_ADC0_3);
    
    MAP_uDMAChannelAttributeDisable(17,
                                    UDMA_ATTR_ALTSELECT | 
                                    UDMA_ATTR_HIGH_PRIORITY | 
                                    UDMA_ATTR_REQMASK);
    
    MAP_uDMAChannelControlSet(17 | UDMA_PRI_SELECT,
                              UDMA_SIZE_16 | UDMA_SRC_INC_NONE | 
                              UDMA_DST_INC_16 | UDMA_ARB_1);
    
    MAP_uDMAChannelControlSet(17 | UDMA_ALT_SELECT, 
                              UDMA_SIZE_16 | UDMA_SRC_INC_NONE | 
                              UDMA_DST_INC_16 | UDMA_ARB_1);
    
    MAP_uDMAChannelAttributeEnable(17, UDMA_ATTR_USEBURST);
}
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void init_uDMA_MIC0()
{
    // adc mic setup
    // uDMA Channel 17
    MAP_uDMAChannelAssign(UDMA_CH17_ADC0_3);
    
    MAP_uDMAChannelAttributeDisable(17,
                                    UDMA_ATTR_ALTSELECT | 
                                    UDMA_ATTR_HIGH_PRIORITY | 
                                    UDMA_ATTR_REQMASK);
    
    MAP_uDMAChannelControlSet(17 | UDMA_PRI_SELECT,
                              UDMA_SIZE_16 | UDMA_SRC_INC_NONE | 
                              UDMA_DST_INC_16 | UDMA_ARB_1);
    
    MAP_uDMAChannelControlSet(17 | UDMA_ALT_SELECT, 
                              UDMA_SIZE_16 | UDMA_SRC_INC_NONE | 
                              UDMA_DST_INC_16 | UDMA_ARB_1);
    
    MAP_uDMAChannelAttributeEnable(17, UDMA_ATTR_USEBURST);
}

adc setup is:

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void init_ADC0()
{
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_ADC0));
    
    ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | 
                      ADC_CLOCK_RATE_HALF, 1);
    
    SysCtlDelay(10);
}
void init_ADC0_MIC0()
{
    MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_2);
    
    MAP_IntDisable(INT_ADC0SS3);
    MAP_ADCIntDisable(ADC0_BASE, 3);
    MAP_ADCSequenceDisable(ADC0_BASE, 3);
    
    MAP_ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_TIMER, 0);
    
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

void init_ADC0()
{
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_ADC0));
    
    ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | 
                      ADC_CLOCK_RATE_HALF, 1);
    
    SysCtlDelay(10);
}

void init_ADC0_MIC0()
{
    MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_2);
    
    MAP_IntDisable(INT_ADC0SS3);
    MAP_ADCIntDisable(ADC0_BASE, 3);
    MAP_ADCSequenceDisable(ADC0_BASE, 3);
    
    MAP_ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_TIMER, 0);
    
    MAP_ADCSequenceStepConfigure(ADC0_BASE, 3, 0, ADC_CTL_CH5 | ADC_CTL_IE | 
                                 ADC_CTL_END);
    
    // ------------------ //
    // Priority Levels
    // Priority 4 = 0xE0 ->lower
    // Priority 3 = 0x60
    // Priority 2 = 0x20
    // Priority 1 = 0x00 ->higher
    // ------------------ //
    
    MAP_IntPrioritySet(INT_ADC0SS3, 0xE0); // Priority 4 !!!
}

start the uDMA channels:

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void start_uDMA_ADC0_SS3()
{
    if (mic0BufferState_PRI == EMPTY)
    {
        MAP_uDMAChannelTransferSet(17 | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, 
                                   (void *)(ADC0_BASE + ADC_O_SSFIFO3), 
                                   &mic0Buffer_PRI, ADC_SAMPLES);
        
        MAP_uDMAChannelEnable(17 | UDMA_PRI_SELECT);
        mic0BufferState_PRI = FILLING;
    }
    
    if (mic0BufferState_ALT == EMPTY)
    {
        MAP_uDMAChannelTransferSet(17 | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, 
                                   (void *)(ADC0_BASE + ADC_O_SSFIFO3), 
                                   &mic0Buffer_ALT, ADC_SAMPLES);
        
        MAP_uDMAChannelEnable(17 | UDMA_ALT_SELECT);
        mic0BufferState_ALT = FILLING;
    }
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void start_uDMA_ADC0_SS3()
{
    if (mic0BufferState_PRI == EMPTY)
    {
        MAP_uDMAChannelTransferSet(17 | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, 
                                   (void *)(ADC0_BASE + ADC_O_SSFIFO3), 
                                   &mic0Buffer_PRI, ADC_SAMPLES);
        
        MAP_uDMAChannelEnable(17 | UDMA_PRI_SELECT);
        mic0BufferState_PRI = FILLING;
    }
    
    if (mic0BufferState_ALT == EMPTY)
    {
        MAP_uDMAChannelTransferSet(17 | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, 
                                   (void *)(ADC0_BASE + ADC_O_SSFIFO3), 
                                   &mic0Buffer_ALT, ADC_SAMPLES);
        
        MAP_uDMAChannelEnable(17 | UDMA_ALT_SELECT);
        mic0BufferState_ALT = FILLING;
    }
}

start stop the ss3

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void start_ADC0_SS3()
{
    MAP_ADCSequenceEnable(ADC0_BASE, 3);
    MAP_ADCIntClear(ADC0_BASE, 3);
    MAP_ADCSequenceOverflowClear(ADC0_BASE, 3);
    MAP_ADCSequenceUnderflowClear(ADC0_BASE, 3);
    MAP_ADCSequenceDMAEnable(ADC0_BASE, 3);
    MAP_ADCIntEnable(ADC0_BASE, 3); // Do I have to do that?
    MAP_IntEnable(INT_ADC0SS3); // Do I have to do that?
    
    MAP_TimerEnable(TIMER2_BASE, TIMER_A);
}
void stop_ADC0_SS3()
{
    MAP_TimerDisable(TIMER2_BASE, TIMER_A);
    
    MAP_IntDisable(INT_ADC0SS3);
    MAP_ADCIntDisable(ADC0_BASE, 3);
    MAP_ADCSequenceDisable(ADC0_BASE, 3);
    MAP_ADCSequenceOverflowClear(ADC0_BASE, 3);
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void start_ADC0_SS3()
{
    MAP_ADCSequenceEnable(ADC0_BASE, 3);
    MAP_ADCIntClear(ADC0_BASE, 3);
    MAP_ADCSequenceOverflowClear(ADC0_BASE, 3);
    MAP_ADCSequenceUnderflowClear(ADC0_BASE, 3);
    MAP_ADCSequenceDMAEnable(ADC0_BASE, 3);
    MAP_ADCIntEnable(ADC0_BASE, 3); // Do I have to do that?
    MAP_IntEnable(INT_ADC0SS3); // Do I have to do that?
    
    MAP_TimerEnable(TIMER2_BASE, TIMER_A);
}

void stop_ADC0_SS3()
{
    MAP_TimerDisable(TIMER2_BASE, TIMER_A);
    
    MAP_IntDisable(INT_ADC0SS3);
    MAP_ADCIntDisable(ADC0_BASE, 3);
    MAP_ADCSequenceDisable(ADC0_BASE, 3);
    MAP_ADCSequenceOverflowClear(ADC0_BASE, 3);
    MAP_ADCSequenceUnderflowClear(ADC0_BASE, 3);
    MAP_ADCIntClear(ADC0_BASE, 3);
    MAP_ADCSequenceDisable(ADC0_BASE, 3);
}

and the record start again and in loop. normaly i dont use the function stop_ADC0_SS3()

here are the interrupt handler

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void ADC0SS3IntHandler(void)
{
    MAP_ADCIntClear(ADC0_BASE, 3); // Do I have to do that?
    MAP_uDMAIntClear(17); // Do I have to do that?
    
    if (MAP_uDMAChannelModeGet(17 | UDMA_PRI_SELECT) == UDMA_MODE_STOP)
    {
        mic0BufferState_PRI = FULL;
    }
    
    if (MAP_uDMAChannelModeGet(17 | UDMA_ALT_SELECT) == UDMA_MODE_STOP)
    {
        mic0BufferState_ALT = FULL;
    }
}
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

void ADC0SS3IntHandler(void)
{
    MAP_ADCIntClear(ADC0_BASE, 3); // Do I have to do that?
    MAP_uDMAIntClear(17); // Do I have to do that?
    
    if (MAP_uDMAChannelModeGet(17 | UDMA_PRI_SELECT) == UDMA_MODE_STOP)
    {
        mic0BufferState_PRI = FULL;
    }
    
    if (MAP_uDMAChannelModeGet(17 | UDMA_ALT_SELECT) == UDMA_MODE_STOP)
    {
        mic0BufferState_ALT = FULL;
    }
}

every time data is sent over spi there is a strong noise in the samples.

0 Charles Tsai over 2 years ago in reply to Kevin Hinrichs

TI__Guru**** 184346 points

Hi,

Although I can't really solve any noise issues for you, I have a few comments that might contribute to the noises you are seeing.

- I see you are running 4 SPI modules at 4.8Mhz. This can create SSO (simultaneous switching output) which can draw quite some currents and affects the voltage supply. Proper decoupling caps and placement of them is critical for high speed operations.

#define SSI_CLOCK (4800000)

- You are using the LaunchPad board. The LaunchPad has VDDA for ADC tied to VDD for simplicity. In another word, any noise on the digital supply can couple to the analog supply for ADC which will affect ADC accuracy. If you were to design your own board, I will suggest you split the supplies to digital and analog domains. ADC VREFP and VREFN are connected to VDDA and GNDA internally. Any noises or ripples on the VDD/GND will follow VREF and hence the accuracy.

- I see you use CH5 for ADC. If you are willing to do an experiment you can try a different ADC channel perhaps with the pin that is far away from the SSI modules or reduce the SSI_CLOCK speed to see if it alleviates your finding. Other than that, I have not much left to offer.

MAP_ADCSequenceStepConfigure(ADC0_BASE, 3, 0, ADC_CTL_CH5 | ADC_CTL_IE |
ADC_CTL_END);

When you create your own design, please go through section 4.5 for ADC design considerations as well as the rest of the document for best design practices.

https://www.ti.com/lit/pdf/spma059

0 Kevin Hinrichs over 2 years ago in reply to Charles Tsai

Prodigy 180 points

I have just tested it. it makes hardly any difference if I send with only one SSI or with 2 or with 3 or with 4. the noise is already present with one data transfer and is amplified by each further data transfer by approx. 5-6dB.

0 Kevin Hinrichs over 2 years ago in reply to Kevin Hinrichs

Prodigy 180 points

I have another EK-TM4C123GXL.
If I use one board for the SPI transmission and the other for the recording of the samples. Can I then separate both boards from one another so that the noise is not transmitted?
But I need a data interface between the boards. So that I can transfer data. And I need between the boards 3-5 GPIO ports as input or output.

0 Charles Tsai over 2 years ago in reply to Kevin Hinrichs

TI__Guru**** 184346 points

Hi,

Kevin Hinrichs said:
If I use one board for the SPI transmission and the other for the recording of the samples. Can I then separate both boards from one another so that the noise is not transmitted?

I think that will help but I believe having a split power rails with VDDA a dedicated supply to ADC will give you the best performance. Don't you plan to design your own board eventually?

3.5.4 Splitting Power Rails and Grounds

Tiva C Series microcontrollers are designed to operate with VDD and VDDA pins connected directly to the same +3.3V power source. Some applications may justify separation of VDDA from VDD to allow insertion of a filter to improve analog performance. Before deciding to split these power rails, the power architecture of the device should be reviewed to determine which on-chip modules are powered by each supply. The device data sheet contains a drawing that shows power architecture. Filter options include filter capacitors in conjunction with either a low-value resistor or inductor/ferrite bead to form a low-pass filter. If the VDD and VDDA pins are split, the designer must ensure that VDDA power is applied before or simultaneously with VDD and that VDDA is removed after or simultaneously with VDD. If VDDA is to be selected as a reference source for the ADC, the ADC will achieve better performance when powered with a separate VDDA power rail and filtered with a 0.01uF and 1uF capacitor (CREF) between VDDA and GNDA. The GND and GNDA pins should always be connected together—preferably to a solid ground plane or copper pour.

Please also check if your PC is providing a stable 5V to the board. Will a different PC or a different USB ports on the same PC make a difference?

0 Kevin Hinrichs over 2 years ago in reply to Charles Tsai

Prodigy 180 points

Charles Tsai said:
Please also check if your PC is providing a stable 5V to the board. Will a different PC or a different USB ports on the same PC make a difference?

I dont use the usb from a pc as power supply. i use a 230V to 5V powersupply from https://www.meanwell.com/productPdf.aspx?i=410#1
Mean Well RS 100-5.

Charles Tsai said:
Don't you plan to design your own board eventually?

Not yet.

I started embedded programming 2 years ago. And I enjoy it. My next goal will be to go deeper into DSP. For this I bought this book:

bcs.wiley.com/.../Books
It uses exactly this board.
The board with the audio codec is in the rebuild.
This is also the reason why it is not bad for me to use 2 boards.
But also in this book he uses 2 SSI to build an I2S data transfer. I find this also very interesting.

But again my question. It doesn't matter if one or four SSI are used at 4.8Mhz. Is there always such a noise when SSI is used?
Or is that just because I am using a transmit line and abusing the SSI connection that way?

0 Charles Tsai over 2 years ago in reply to Kevin Hinrichs

TI__Guru**** 184346 points

All I can say is that crosstalk varies with transmission frequency, with higher frequencies creating more interference. I would have expected at lower SPI clock frequency, any noise induced on ADC SPI from SPI will be reduced. The accuracy of ADC will be affected by how VDDA is sourced and noise on single-ended input from the nearby digital traces. Single-ended inputs are more sensitive to board and trace noise than differential inputs. Single-ended inputs are highly dependent on how clean the board layout is designed. If the input signal is not well-isolated on the board, higher noise could potentially be seen at the ADC output. As I have already suggested you can improve the ADC accuracy by splitting VDDA for ADC and you can use the differential ADC mode. As for the LaunchPad, it is what it is today.

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Arm-based microcontrollers forum

EK-TM4C123GXL: EK-TM4C123GXL during send SPI data than have on Analog input rms -30db noise