Other Parts Discussed in Thread: AM2434, , SYSCONFIG
hi,
I am trying to use the L1 FIFO of the MII_G_RT module on PRU1 on ICSSG0 of the AM2434 on the TMDS243EVM board. Unfortunately I cannot get the FIFO to share its content with the outside world.
I use the following code on PRU1:
#include <stdint.h> // uint8_t, uint16_t, ...
#include <pru_cfg.h>
#include <pru_mii_rt.h>
#include <pru_mii_g_rt.h>
volatile register uint32_t __R30;
volatile register uint32_t __R31;
uint32_t fill_level, data, status, control;
void main(void)
{
// initial config
CT_CFG.spp_reg_bit.xfr_shift_en = 1; // enable GP SP r0 32-bit shifting feature
CT_CFG.gpcfg1_reg_bit.pr1_pru1_gp_mux_sel = 2; // select MII mode
// general configuration MII
CT_MII_RT.txcfg0_bit.tx_enable0 = 0; // disable TX0 PORT
CT_MII_RT.txcfg1_bit.tx_enable1 = 0; // disable TX1 PORT
CT_MII_RT.txcfg0_bit.tx_mux_sel0 = 0; // select PRU0 for TX0
CT_MII_RT.txcfg1_bit.tx_mux_sel1 = 1; // select PRU1 for TX1
// configure MII TX1
CT_MII_RT.txcfg1_bit.tx_auto_preamble1 = 0; // PRU inserts custom pre-amble
CT_MII_RT.txcfg1_bit.tx_byte_swap1 = 0; // no byte swap
//CT_MII_RT.txcfg1_bit.tx_32_mode_en1 = 1; // enable auto push with R30
// CT_MII_RT.txcfg1_bit.tx_ipg_wire_clk_en1 = 0; // dont care about inter package gap
//CT_MII_RT.txcfg0_bit.tx_ipg_wire_clk_en0 = 0; // same settings must apply for TX0 PORT
CT_MII_RT.txcfg1_bit.tx_start_delay1 = 0; // no start delay
CT_MII_RT.txcfg0_bit.tx_start_delay0 = 0; // no start delay
CT_MII_RT.txcfg1_bit.tx_clk_delay1 = 0; // no delay
CT_MII_RT.txcfg0_bit.tx_clk_delay0 = 0; // no delay
CT_MII_RT.tx_ipg1_bit.tx_ipg1 = 16; // 16 cycles delay between packets
// ...
CT_MII_RT.txcfg0_bit.tx_enable0 = 1; // enable TX0 PORT (?)
CT_MII_RT.txcfg1_bit.tx_enable1 = 1; // enable TX1 PORT (?)
// configure MII_G TX1
CT_MII_G_RT.icss_g_cfg_bit.mii1_mode = 1; // RGMII mode
CT_MII_G_RT.icss_g_cfg_bit.tx_l2_en = 1; // enable TX L2 FIFO
CT_MII_G_RT.icss_g_cfg_bit.tx_l1_en = 1; // enable TX L1 FIFO
// start sending bytes
//__R31 |= (1 << 18); // reset RX
__R31 |= (1 << 30); // reset TX
fill_level = CT_MII_RT.tx_fifo_level1_bit.tx_fifo_level1; // read nibble cnt in FIFO (should be zero)
// fill FIFO with some data
data = 0xFFFFFFFF;
__xout(40, 2, 0, data);
__xout(40, 2, 0, data);
__xout(40, 2, 0, data);
fill_level = CT_MII_RT.tx_fifo_level1_bit.tx_fifo_level1; // read nibble cnt in FIFO
__R31 |= (1 << 29); // TX EOF
// L1 FIFO seems not to start ...
while(1)
{
fill_level = CT_MII_RT.tx_fifo_level1_bit.tx_fifo_level1;
__xin(40, 19, 0, status);
}
}
I can see that the FIFO gets filled by checking CT_MII_RT.tx_fifo_level1_bit.tx_fifo_level1. I also see that the L2 FIFO has pushed the data to the L1 FIFO by reading the status via __xin(40, 19, 0, status);. However, the L1 FIFO seems to never push out its data on the signal lines TXD0-3. TXEN never gets high. The TRM lists a few conditions for the TX_EN to rise:
"
There are four dependencies that must be true for TX_EN to assert.
1. TX L1 FIFO not empty
2. Interpacket gap (IPG) timer expiration
3. RX_DV to TX_EN timer expiration
4. TX_EN compare timer expiration
"
I assume that all of them are either met or irrelevant for my use case. I am not interrested in a pre-amble, CRC or receiving anything, I just want the FIFO to output the bytes loaded into it. As far as I know, if I yould use the MII mode then there is a 25MHz clock needed as an input, however I use the RGMII mode (CT_MII_G_RT.icss_g_cfg_bit.mii1_mode=1), so the chip should use its internal RGMII clock (= MAIN_PLL0_HSDIV4).
Below a picture of my pin configuration:
I checked with the oscilloscope that TXD0 (W4) and/or TXEN (U5) never rise. Also I would expect CT_MII_RT.tx_fifo_level1_bit.tx_fifo_level1 to decrease anyway.
Can someone please help me to get this to work. Thank you.
Kind regards,
Martin
