TMDSIDK437X: How to assert MII_RT MAC signal TX_EN?

Junke Hu

Part Number: TMDSIDK437X

hi,

am working on a demo of PRUSS1 MII_RT to send packet from PRU0 through mii0 port, I can push data into TX FIFO, but can't transmmit data out to phy. I've checked the signal of mii and found that the signal TX_EN is always low, and I think that's why the data remains in FIFO.

So I want to know the steps to assert TX_EN.

I've found the notes in TRM:

There are four dependencies that must be true for TX_EN to assert.
1. TX L1 FIFO not empty
2. Interpacket gap (IPG) timer expiration
3. RX_DV to TX_EN timer expiration
4. TX_EN compare timer expiration

But I don't understand what's the TX_EN timer? and is there any way to check wether the 3 mentioned timers expiried or not?

Here is my demo code

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#include <stdint.h>
#include <pru_cfg.h>
#include <pru_ctrl.h>
#include "pru_mii_rt.h"
#define PKT_SIZE    70
volatile register uint32_t __R30;
volatile register uint32_t __R31;
uint8_t buffer[PKT_SIZE] = {
        0xf0, 0xde, 0xf1, 0x9f, 0xbb, 0x91,
        0x2c, 0x6b, 0x7d, 0xb3, 0xf8, 0x56,
        0x08, 0x00, 0x01, 0x02, 0x03, 0x04,
        0x05, 0x06, 0x07, 0x08, 0x09, 0x0a,
        0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10,
        0x11, 0x12, 0x13, 0x14, 0x15, 0x16,
        0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c,
        0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22,
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

#include <stdint.h>
#include <pru_cfg.h>
#include <pru_ctrl.h>
#include "pru_mii_rt.h"


#define PKT_SIZE    70

volatile register uint32_t __R30;
volatile register uint32_t __R31;


uint8_t buffer[PKT_SIZE] = {
        0xf0, 0xde, 0xf1, 0x9f, 0xbb, 0x91,
        0x2c, 0x6b, 0x7d, 0xb3, 0xf8, 0x56,
        0x08, 0x00, 0x01, 0x02, 0x03, 0x04,
        0x05, 0x06, 0x07, 0x08, 0x09, 0x0a,
        0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10,
        0x11, 0x12, 0x13, 0x14, 0x15, 0x16,
        0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c,
        0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22,
        0x23, 0x24, 0x25, 0x26, 0x27, 0x28,
        0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e,
        0x2f, 0x30, 0x31, 0x32, 0x33, 0x34,
        0x35, 0x36, 0x37, 0x38
};


void mii_rt_init(void)
{
    CT_CFG.GPCFG0_bit.PRU0_GPI_MODE = 0x3;//mii_rt mode
    CT_CFG.SPP_bit.XFR_SHIFT_EN = 0x1;//enable

    MII_RT.RXCFG0_bit.RX_CUT_PREAMBLE = 0x1;
    MII_RT.RXCFG0_bit.RX_ENABLE = 0x1;//enable mii0 rx


    MII_RT.TXCFG0_bit.TX_CLK_DELAY = 0x6;// to ensure IO timing
    MII_RT.TXCFG0_bit.TX_START_DELAY = 0x40;//delay 320ns after rx_dv active
    MII_RT.TXCFG0_bit.TX_MUX_SEL = 0;//set mii0 tx data from PRU0 (default PRU1)
    MII_RT.TXCFG0_bit.TX_AUTO_PREAMBLE = 0x1;//tx fifo provides preamble
    MII_RT.TXCFG0_bit.TX_ENABLE = 0x1;//enable mii0 tx
}

void test_tx_push_fifo()
{
    uint8_t i;
    for(i=0; i<PKT_SIZE; i++){
        __R30 = buffer[i];
        __R30 |= (uint32_t)(0xff<<16);
        __R31 |= (1<<24);
    }
}

/**
 * main.c
 */
int main(void)
{
    mii_rt_init();

    __R31 |= (1<<30);//tx reset

    while(1){
        test_tx_push_fifo();
        __R31 |= (1<<29);//set TX EOF
        __delay_cycles(20000);
    }

	__halt();

    return 0;
}

over 4 years ago

0 Junke Hu over 4 years ago

Prodigy 60 points

Some more details.

1. During debug, I read the R31 register to find its value is always 0x1000000 (bit24 set)

2. While TX_EN_MODE is enabled, TX_ENABLE is NOT self cleared when TX_EOF cmd set.

0 Nick Saulnier over 4 years ago in reply to Junke Hu

TI__Guru* 93105 points

Hello Junke,

Are you writing custom PRU Ethernet firmware? TI already provides PRU Ethernet firmware and drivers. Let us know what operating system your ARM core is running and we can point you to the appropriate resources.

Regards,

Nick

0 Junke Hu over 4 years ago in reply to Nick Saulnier

Prodigy 60 points

hi Nick,

yes, am writting a custom PRU firmware.

and now I just want to verify the function of MII_RT transmit under CCS, so the ARM core is not running any OS.

What I did under CCS is create a project based on board AM437x IDK, with a default target config. The firmware code is as shown before. And when debug, I first connect the ARM core and run script PRU_ICSS_Init, then disconnect ARM and connect PRUICSS1 PRU0. After all this, I start debug run.

I am sure that the tx data has been pushed into TX FIFO by watching the MII_RT.TXFLV0 register, which shows there are 0x80 nibbles, that is 64 bytes, in the FIFO, but the data never transmit out due to the lack of TX_EN signal. It seems like the MII_RT is not working at all.

So, is there any steps I missed? And can you tell me what's the TX_EN compare timer that TX_EN assertion depends on for I didn't find any details in TRM?

thanks.

0 Nick Saulnier over 4 years ago in reply to Junke Hu

TI__Guru* 93105 points

Hello Junke,

I am going to reassign this to another team member. Please keep in mind that we do not provide in-depth support on the forums for customers writing custom Ethernet protocols. So we may be limited in the help we can offer.

Regards,

Nick

0 Junke Hu over 4 years ago in reply to Nick Saulnier

Prodigy 60 points

hi Nick,

Thanks for your help.

I'll be waitting.

0 Roopak Houji over 4 years ago in reply to Junke Hu

TI__Prodigy 360 points

Hi Junke

1. RX_DV to TX_EN timer expiration
you can keep TX_START_DELAY to zero i.e. MII_RT.TXCFG0_bit.TX_START_DELAY = 0x0;

2. TX_EN compare timer expiration
This is only applicable for Time Triggered send mode using CMP3 and CMP4.not applicable for current use case

- We would like to know one point from your end , Are you configuring the pinmux for the ICSS pins?

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TMDSIDK437X: How to assert MII_RT MAC signal TX_EN?