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Hi All,
I am using TMS570LC43 MCU with safeTI Diagnostic Library and integrate with RTOS.
In afterSTC() function
Code reach to the SL_SelfTest_VIM(VIM_SOFTWARE_TEST); function and fail inside this function.
Here the inside the "tmp = SL_SelfTest_CCMR5F(CCMR5F_CPUCOMP_ERROR_FORCING_TEST, TRUE, &failInfoCCMR5F);"
*ccmr5fKeyReg = CCMR5F_CCMKEYR_MODE_ERRFORCING; <-- the value inside "CCMkeyR1" register 0xfffff604 is 0
while (CCMR5F_CCMKEYR_MODE_LOCKSTEP != (*ccmr5fKeyReg & CCMR5F_CCMKEYR_MODE)) {
stuck here and system is going to SW reset.
}
Can you please tell what is the reason behind that, we have already did viminit();
Both SL_SelfTest_VIM(VIM_SOFTWARE_TEST); and SL_SelfTest_DMA(DMA_SOFTWARE_TEST); failing
Thanks
Pankaj Verma
Hi Pankaj,
We started working on your thread and will provide an update soon.
--
Thanks & regards,
Jagadish.
Hi Pankaj,
First of all, I hope you are using "FreeRTOS" not "TI RTOS", because "TI RTOS" will not supported by hercules devices.
And again, we never tested "SafeTI Diagnostic Library with "FreeRTOS" either.
Just make sure the error is not related to the below bug:
If still issue persists, please attach your complete project so that i can debug the project at my end once. You can even do a private message, so that no one can see the code.
--
Thanks & regards,
Jagadish.
Hi Jagadish,
I am using Safe RTOS which is license based.
So for me it is not possible to share my project.
simultaneously, i will make another project based on free RTOS and integrate safeTI diagnostic library and i will share with you.
I have debug that the buffer sl_priv_flag_set[57], the bit number 57 and 11 is 1.
this issue is not related with shared thread.
i am shearing some image's for your reference
i have seen that below code is stuck in while condition.
while (CCMR5F_CCMKEYR_MODE_LOCKSTEP != (*ccmr5fKeyReg & CCMR5F_CCMKEYR_MODE)) {
stuck here and system is going to SW reset.
}
case CCMR5F_CPUCOMP_ERROR_FORCING_TEST: case CCMR5F_CPUCOMP_ERROR_FORCING_TEST_FAULT_INJECT: case CCMR5F_VIMCOMP_ERROR_FORCING_TEST: case CCMR5F_VIMCOMP_ERROR_FORCING_TEST_FAULT_INJECT: case CCMR5F_PDCOMP_ERROR_FORCING_TEST: case CCMR5F_PDCOMP_ERROR_FORCING_TEST_FAULT_INJECT: case CCMR5F_INMCOMP_ERROR_FORCING_TEST: case CCMR5F_INMCOMP_ERROR_FORCING_TEST_FAULT_INJECT: retVal = TRUE; regBkupIntEnaSet = esmREG->IESR1; regBckupErrInfulence = esmREG->EEPAPR1; SL_FLAG_SET(testType); if(_sl_fault_injection == FALSE) { /*flag is set to indicate the current test which is ongoing and These flags are used in the sl_esm.c so as to mask the esm callback*/ esmREG->IECR1 = GET_ESM_BIT_NUM(ESM_G1ERR_CCMR5_SELFTEST); esmREG->DEPAPR1 = GET_ESM_BIT_NUM(ESM_G1ERR_CCMR5_SELFTEST); } *ccmr5fKeyReg = CCMR5F_CCMKEYR_MODE_ERRFORCING; while (CCMR5F_CCMKEYR_MODE_LOCKSTEP != (*ccmr5fKeyReg & CCMR5F_CCMKEYR_MODE)) { }
Can we arrange a teams call so we will discuss in detail.
Thanks
Pankaj Verma
Hi Pankaj,
With debugger connected, CCMR5F is disabled so do not run when debugger is connected.
HI Wang,
OK "With debugger connected, CCMR5F is disabled so do not run when debugger is connected."
My concern is:-
I am always run safeTI demo code in debug mode only. and that TI demo code run properly. (<--- without RTOS)
All the initialization and self test case execute properly. "debug mode only"
Only 1-2 test case was failed otherwise all the test case run properly. " debug mode only"
In my code only i am facing CCMR5F problem. (<--- with RTOS).
SL_SelfTest_VIM(VIM_SOFTWARE_TEST); failed
I will try without debugger and let you know, but i think this is not a solution.
Thanks
Pankaj Verma
SL_SelfTest_VIM(VIM_SOFTWARE_TEST); failed
SL_SelfTest_CCMR5F(..) is called by SL_SelfTest_VIM(..) for VIM SW test.
From TMS570LC4357 TRM (Page 507):
13.2.5 Operation During CPU Debug Mode
Certain debug operations place the CPU in a halting debug state where the code execution is halted.
Because halting debug events are asynchronous, there is a possibility for the debug requests to cause
loss of lockstep. CCM-R5F will disable all functional diagnostics upon detection of halting debug requests.
Core compare error will not be generated and flags will not update. A CPU reset is needed to ensure the
CPUs are again in lockstep and will also re-enable the CCM-R5F
Hi Wang,
I am not understanding that if debug mode is the issue.
In demo code is working fine.
But in my code (safeRTOS with safety lib) while in debug mode SL_SelfTest_VIM(VIM_SOFTWARE_TEST); and SL_SelfTest_DMA(DMA_SOFTWARE_TEST); is failing..
For now i have comment SL_SelfTest_VIM(VIM_SOFTWARE_TEST); and SL_SelfTest_DMA(DMA_SOFTWARE_TEST); line.
for check the rest of the code
I have seen that the in xTaskStartScheduler( pdTRUE );
/* Start the first task. */
portSTART_FIRST_TASK(); <-- failing here
and going into
resetEntry
b _c_int00
b vUndefAbort
b vSafeRTOSSVCHandler <-- here first
b vPrefetchAbort
b vDataAbort <-- than here.
b phantomInterrupt
ldr pc,[pc,#-0x1b0]
ldr pc,[pc,#-0x1b0]
I am not understand why the portSTART_FIRST_TASK(); failing here.
Can you please support.
Thanks
Pankaj Verma.
Hi Pankaj,
The Debug Mode here is not the CCS "Debug" mode. It means the mode when the debugger is plugged onto the JTAG header.
Hi Wang,
Yes you are correct.
But when i am connect debugger to EVK board JTAG header and run target board. It is working fine and all the self test case execute properly.
reset_reason variable value is RESET_TYPE_DEBUG.
Here it is passing all test case.
In my scenario
it is not working. same process i am following.
Can you please see the code which i have shared with Jagadish. (specially Linker file, HL_sys_intvecs.asm and startup file)
Thanks
Pankaj Verma
H Pankaj,
Thanks for sharing the code with us. Is the shared code a CCS working project except for the selftest failure? I will find the shared project, and try it on my bench after I am back from my travel..
HI Wang,
Yes the shared project is working in CCS environment except self test failure.
Inside HL_sys_startup.c
I have create some macro for your reference
/* USER CODE END */
#define SL_STARTUP_FORMAT1 1 <-- this macro is for self test startup code reference from demo code
#define SL_STARTUP_FORMAT2 0 <-- this macro for Helcogen selftest startup code "you can ignore this"
#define FREERTOS_DEF. <-- this macro is for "if you want to run freeRTOS code without selftest code"
Thanks
Pankaj Verma
HI Pankaj,
I searched my email, but I could not find the link for the source code. Checking with Jagadish about the your source code.
HI Pankaj,
I you your code on my Launchpad, but it causes reset repeatedly. The code doesn't jump to VIM selftest.
HI Wang,
In my code, if you using safeTI lib yes, it is reset initially.
After debug reset 2/3 times it iwill show debug_reset. It will go after_stc() function..
RTOS code is working properly without using safetI code.
In my side if i am active #define FREERTOS_DEF. macro RTOS code is activated (withpout safeTI code/lib) and code is working properly.
#define FREERTOS_DEF 1
Inside HL_sys_startup.c
I have create some macro for your reference
/* USER CODE END */
#define SL_STARTUP_FORMAT1 0 <-- this macro is for self test startup code reference from demo code
#define SL_STARTUP_FORMAT2 0 <-- this macro for Helcogen selftest startup code "you can ignore this"
#define FREERTOS_DEF 1 <-- this macro is for "if you want to run freeRTOS code without selftest code"
If we are using safeTI lib code then we are facing reset and initialization problem and RTOS scheduling problems
Please activate above macro and see the result.
Still facing any problem please let me know.
we will discuss on teams and show you in my side also..
Thanks
Pankaj Verma
In my code, if you using safeTI lib yes, it is reset initially.
After debug reset 2/3 times it iwill show debug_reset. It will go after_stc() function..
I knew this. It is expected. The CPU selftest and STC selftest issue a CPU reset after completion of the test regardless of pass or fail.
I got reset in a random location of after_stc() function.
To run the SDL function, the MCU has to be in privilege mode.
Hi Wang,
Is the code is working with (freertos+safeTI lib) at your end?
If yes, please let me know what is the issue?
Any processor mode other than User mode is privilege mode. And i have checked that our code is run in Supervisor mode"Privilege mode" only.
Hi Wang,
At my side also when i am running code without SDL than code is working fine all the task and schedular start properly.
But if i am using SDL with RTOS than i am also facing reset problem at VIM self test, and schedular start.
I don't have a working freeRTOS + SDL example. I am not sure if the issue is caused by MPU settings in freeRTOS.
I developed an example of using SDL in freeRTOS. There are two tasks in my example. One task toggles one GPIO pin in user mode, and another performs CAN RAM ECC/Parity selftest in privileged mode (system mode).
The flash related selftest has to be executed from SRAM, so the APIs are copied to one section of SRAM, and the MPU region for this RAM section can’t be configured as “Execute Never”. Some selftests have to be executed in privileged mode. The mode is switched to system mode before doing selftest in task2 and switched back to user mode after the selftest is done.
The example has been tested on my TMS570LC43x launchpad and HDK. I have shared the example in TIDrive with you.
HI Wang,
Thanks for your support.
We are working on it and checking. we will update you soon.
One question i have
What is the use if SafeTILib_TMS570LC43_BE.lib file?
What it is have in this lib file and Is this file is necessary to use for run safeTI functionality?
Please let us know.
Thanks
Pankaj Verma
It is the SDL library for TMS570LC4357. You can use either the library or the source code (sl_selftest.c, and other c or asm files). My example project doesn't link this library.
Thanks Wang,
We have tried your code. The code is running but i think checkPLL1Slip() function is disturbing the system tick so that the execution of task timing is not accurate.
SO i have checked in my code also. I have seen that the before using SDL the tick was 1ms. After using SDL with checkPLL1Slip() the tick is 20 ms.
which is not correct. Can you please check once again.
Can you please share the code section of void vPortEnablePrivilegedMode( void );
I did not find in code where it is located.
Thanks
Pankaj Verma
.
checkPLL1Slip() intentionally generates PLL slip by changing the PLL Multiplication Factor. The GCM clock source is switched to OSCLK which is much slower than the clock from PLL output. But the GCM clock source is restored back to normal at the end of checkPLL1Slip() function.
vPortEnablePrivilegedMode() is mapped to the Software interrupt vector using a SWI_ALIAS pragma of the TI compiler.
The software interrupt ISR (vPortSWI) is defined in os_portosm.asm:
Please refer to this article for SWI_ALIAS pragma:
http://downloads.ti.com/docs/esd/SPNU151/the-swi-alias-pragma-spnu1513554.html