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MSPM0G3507: SYSPLL startup waits endless for PLL stabilization in while loop

Part Number: MSPM0G3507
Other Parts Discussed in Thread: SYSCONFIG

I am using 'gpio_toggle_output_LP_MSPM0G3507_nortos_ticlang' project example (MSPM0 SDK 1.0.1.03, SysConfig 1.16.1, XDCtool 3.62.1.16_core).

I am trying to use SYSPLL to clock CPU with 80MHz.

When I change the clock configurationusing Clock Tree

HFXT = 40MHz, EXHFMUX = XTAL, SYSPLL.SYSPLLMUX = HFCLK, SYSPLL.PDIV = /1, SYSPLL.QDIV = X4, SYSPLL.CLK0_DIV = /2, HSCLKMUX = SYSPLL0, MDIV = /1, SYSCTLMUX = MDIV

then MCLK = 80MHz

But the example code gets stuck in below while loop in the routine DL_SYSCTL_configSYSPLL()

    // wait until SYSPLL startup is stabilized
    while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) !=
           DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) {
        ;
    }

Any help will be highly appreciated.

Note: when after Clock Tree I go back to SysConfig and uncheck "Use Clock Tree", then there is "Resource conflict" for HFXIN and HFXOUT. Regardless switching from "Clock Tree" to SysConfig, seems Clock Tree and SysConfig block each other. Once used "Clock Tree" I MUST use is, else there is SysConfig error:
error: /ti/driverlib/SYSCTL peripheral.hfxInPin: Resource conflict
    PA5/45 is only valid on the signal SYSCTL.HFXIN which is in use by HFXT(/ti/clockTree/pinFunction.js) peripheral.hfxInPin and is also in use by HFXT(/ti/clockTree/pinFunction.js) peripheral.hfxInPin
error: /ti/driverlib/SYSCTL peripheral.hfxOutPin: Resource conflict
    PA6/46 is only valid on the signal SYSCTL.HFXOUT which is in use by HFXT(/ti/clockTree/pinFunction.js) peripheral.hfxOutPin and is also in use by HFXT(/ti/clockTree/pinFunction.js) peripheral.hfxOutPin

Thanks & Regards

Nikolai

  • Hi Nikolai,

    Here's a previous thread with information relating to this. Currently, in Sysconfig, a check is done for the SYSOSC clock, but when using an external clock the SYSOSC is turned off. When the IDE resets the device, it doesn't go into a reset state low enough to reconfigure the clock states, so the device will still use the HFXT. We are going to implement a change to the clock check in the next SDK release.

    In the meantime, you can recreate the function call and overwrite the check. One way is to check if the HFXT is being used already and forgo the next set of checks. All sysconfig functions have the weak attribute which will allow you to use the same function name.

    I will create an example that can be used as a workaround tomorrow and post it here.

    Regards,

    Luke

  • Hi Luke, are any workaround examples available?

    Regards

    Nikolai

  • After Update to CCS 12.4.0.00007 and SysConfig 1.17.0 and after manuall clean-up in syscfg file (because of conflicts with Clock Tree) I can configur by SysConfig (not by Clock Tree!) for using SYSPLL and external OSC 40 MHz

  • Hi Nikolai,

    Sorry, I was gone last week and am now looking into this.

    Did you also update to the latest sdk (1.10) when you updated the CCS and Sysconfig versions?

    Using the latest SDK I am not able to replicate this anymore, but can when I go back to 1.00.0.04.

    Regards,

    Luke

  • Hi Luke, also after update to sdk 1.10 it works as expected.

    One clue is, by SysConfig I can configur "ULPCLK Divider" = 1 and thus set ULPCLK = 80MHz. But by "Clock Tree" this causes an error "ULPCLK is limited to below 40MHz". When I change "ULPCLK Divider" = 2, then it works too

    Thank you!

    Nikolai