MSPM0G3507: Unable to use SYSPLL to clock CPU

Hi Vijaya,

I have tested your settings with SYSPLLCLK2x set to 40MHz and sourcing to MCLK, with UART3: 4 Mbps, 8x oversampling and using the uart_tx_multibyte_fifo_dma_interrupts example.

Please enable the "check for clock stabilization" setting that is in SYSCTL. When this was not enabled the program would wait at while(false ==gDMADone).

Regards,

Luke

Hi Luke,

Thanks a lot for quickly checking this.

I enabled "check for clock stabilization". But the data that is coming out on Tx line is not correct. Mostly it is some junk data with framing errors. When you tested, did you get chance to verify the data that is coming out on Tx? 

I didn't see any problem reported in errata related to PLL. This is the 4th sample I am testing. But overall I think, when PLL is used, system is not stable and results are not consistent.

Thanks & Regards

Vijaya

Hi Vijaya,

I was using a logic analyzer to verify the data, below is a screenshot of the scope. I have tested on 2 different launchpads with UART3 on PA25 and PA26. The clock stabilization check is used to verify that the clock system is stable and consistent.

1. What pins are you using for your UART?
   1. Verify that there are not jumpers populated that are associated with the pins, for example if you're using PA26 make sure J3 is unpopulated on the bottom of the board. Also verify that the word length, parity, stop bits, baud rate, and significant bit on your analyzer are the same as the MSPM0.
2. Can you send a screenshot of your TX data and the .syscfg file? I want to see what results you are getting and to double check that our settings are the same.
3. Which SDK version are you using?

Regards,

Luke

Hello Luke,

Please see my response below. How to share the sysconfig file in this forum? Tried using insert->image/video/file. But unable to upload it.

1) I am not using the the Launch pad. We got MSPM03507 (LQFP-64) samples and made breakup boards with these ICs with an intention to use them in our target boards. I am using pin 6 (Rx) and 7 (Tx) for UART3.  I am testing the breakup boards in both ways...i.e. powering them separately or connecting them to final hardware.

  I am using J-Link Plus Debugger to connect to SWD interface.

2) Attaching the screen shots of logic analyzer captures  in both working and non working case. (Logic analyzer settings are same in bot cases)

         Working case (No SYSPLL,  CPU clock - 32MHz, 4Mbps Baud rate, Oversampling 8)

          Failed case (SYSPLL2x enabled, CPU clock -40MHz, 4Mbps Baud rate, Oversampling 8)

Code is exactly same as the one used in the example  'uart_tx_multibyte_fifo_dma_interrupts_LP_MSPM0G3507_nortos_ticlang' except for changes to UART3 references.

3) I am using mspm0_sdk_0_56_00_01_eng SDK.

Please let me know if you need more details.

Thanks & Regards

Vijaya

Hi Vijaya,

It looks like the baud rate is off and case with 40MHz clock is faster. It looks like you're using the Saleae, there should be an auto-baud rate detection if you want to see what the baud rate is getting sent.

I'm attaching my project with the UART3 using pins 6 and 7 at 4Mbps and MCLK, ULPCLK at 40MHz. Can you import and run this?uart3_4Mbps.zip

Using insert -> image/video/file then clicking the upload button should load your file explorer, from there navigate to the project and select the .syscfg file.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/uart_5F00_tx_5F00_multibyte_5F00_fifo_5F00_dma_5F00_interrupts.syscfg

Regards,

Luke

Hi Luke,

I couldn't find auto baud setting in Saleae, so I manually calculated the baud rate (as suggested by Saleae). It is coming as 4.762Mbps. When I used this baud rate setting then data is appearing properly on logic analyzer. I think, for some reason, UART is not working at set baud rate.

So far, I am unable to use the project you sent. Somehow I am not able to download to the target even after changing the debugger connection to 'SEGGER J-Link Emulator'. I need to look into this. But a quick look at .syscfg shows, in my project I used clock tree to configure clock settings and enabled 'use clock tree'. Where as I think you did clock settings in a different way. 

I am attaching the project I used here.   uart_tx_multibyte_fifo_dma_interrupts_LP_MSPM0G3507_nortos_ticlang.zip

Please let me know if you need more details.

Thanks & Regards

Vijaya

Luke,

I used the .syscfg file you shared in my project, and things started to work. UART is transmitting data at set baud rate.

As I mentioned above, the only difference is I used clock tree to configure clock and checked 'use clock tree' under SYSCTL. Where as in .syscfg you shared,  the same clock settings were done directly in SYSCTL. Clock setting wise, I don't see any difference in both cases. But when I used clock tree things are not stable.

Thanks & Regards

Vijaya

Luke,

Even though the clock setting are same when configured through SYSCTL and Clock Tree, some how the generated code is different. And when I used clock tree, then SYSPLL is not stable. Is there a problem with using clock tree?

I am moving from sample codes to my actual application code. Just to conclude on this, if there is a problem with clock tree then I will refrain from using it in my program. If there is a problem with PLL itself then, I will stick to internal/external clock without using PLL. Or am I missing anything?

Thanks & Regards

Vijaya

Hi Vijaya,

You are right the clock tree is generating the wrong set of code, we will be fixing this in a future update. Using the SYSCTRL will be the best for your development currently.

Regards,

Luke