AM2432: QSPI flash configuration for QSPI boot

Our qspi is on a bus that is also connected to a OSPI Nor flash where they have different chip selects, and that flash is working as expected. I have been trying all kinds of different parameters in the flash config table. We have also changed the clock rate from 133 MHz with divisor 4 to 200 MHz with devisor 4 for the 50 Mz qspi boot requirements. The 1s-1s-1s protocol works for the flash_IO example, but not the 1s-1s-4s. In the uniflash, nether protocol can be  used

Hi Jacob,

I see some mismatches between the JSON data generated by the flash diag and the configuration you're showing in SysConfig. Did you do any manual updates? I am specifically interested in the QE Type. I see that you have it updated in the sysconfig as 3. Did you get that data from the flash datasheet? Because if the QE type is incorrect, 1-1-4 mode won't be enabled correctly. Let me get back to you after checking the flash datasheet.

Regards,
Anand Mahadevan SS

Yes I did try some manual changes after the first import didn't work. I was looking at the datasheet, but I was not sure about that one and the QPI Sequence. I have tried both with the exact after uploaded, and a handful of other variations. 

Thank you for your help

Hi Jacob,

After going through the datasheet, what I can see is that the quad enable requirements are zeroed out, which means that it might be enabled by default or detects based on instruction. In this case you should set the QE type as 0 itself. This is for 1-1-4 mode. Let me know if the configuration worked.

Regards,
Anand Mahadevan SS

Hello, I can confirm that that did not resolve the issue. Is there anything else you can think of?

Hello. Is there a way I can get some dedicated support for getting this working? As in is there somewhere else that I should reach out to? My company is needing to verify that the processor is able to support the qspi flash, and that the board we have is functioning as expected.

Hi Jacob,

Can you let me know what is the data mismatch? Is it data missing, or data shifted by some bytes or something else? If you can post the values of the Rx and Tx buffers in the example after the transfers before the comparison, that would be helpful. Because it is possible that there is a timing issue here. That can be adjusted with dummy cycles and read capture delay settings.

Regards,
Anand Mahadevan SS

For the first write to flash, the tx buffer counts up from 0 to 255 and repeats. This is the rx_buffer after the first read attempt: 

The read buffer has the same contents after the second read as well. 

I tried turning off DMA to see if that made a difference, and it did not. 
Changing the read busy mode from Legacy to the SR bit 7 also did nothing.

Changing the timing to the following:

Resulted in contents: 

Update: I got the flash IO to pass with setting the write command to 0x32 and dummy cycles to 8, but the bootloader (running uart_uniflash) still doesn't work

Update, got qspi flash to work. will post solution tomorrow

edit: Flash now opens, and in the flash_io example, it passes, but only without any ddr configured. The uart uniflash fails if ddr is not configured (the entire image after uniflash gets sent, but 100 percent, there is a getchar timeout) and if the ddr is configured the ospi flash does not open.

So I was able to preform a read/write on the qspi flash device, by using the write program command 0x32, with qspi enable 11000, but it still will not work on uart uniflash. OSPI init fails if DDR is configured, or if MMCSD has the default clock rate. It is not successfully flashing. 

Hello. I need help on this. The flash open works in uart uniflash, but after the app image is sent, the bootloader gets a error message after the image is sent

This problem is urgent for my company, please assist.

Please view this thread and / or get someone else to. I am still waiting on support. 

Hi Jacob,

My apologies for the late response. I understand that you have a working flash driver but uart_uniflash is not successful. Before we look into it, can you tell me why DDR is being enabled? I thought that you wanted 1-1-4 protocol? You don't need to enable DDR for that. Or are you using 4D-4D-4D protocol? Also can you post the exact error logs of flashing here? Also I am not sure why UART uniflash fails to work if DDR is not configured. If you're using the same 1-1-4 protocol in all examples including the sbl_uart_uniflash, that error shouldn't come. Please send over the changed example.syscfg files for the sbl_uart_uniflash project as well. I can review and get back to you.

Regards,
Anand Mahadevan SS

Uart_uniflash requires the DDR to be configured in my understanding, because it writes the image into DDR through DMA before transferring it into flash. I am using 1-1-4 protocol. There are no error logs printed when the DDR is enabled, because it gets to Flash_Open() and just gets stuck waiting for the flash status 

This is in the ospi_flash_io project with DDR enabled as an attempt to isolate the issue that is being caused. If DDR is not configured it passes fine, but if it is, it fails.  Here is the sysconfig for the ospi_flash_io project with the DDR enabled.  

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM243x@08.06.00"
 * @versions {"tool":"1.17.0+3128"}
 */

/**
 * Import the modules used in this configuration.
 */
const flash      = scripting.addModule("/board/flash/flash", {}, false);
const flash1     = flash.addInstance();
const ddr        = scripting.addModule("/drivers/ddr/ddr", {}, false);
const ddr1       = ddr.addInstance();
const udma       = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1      = udma.addInstance();
const clock      = scripting.addModule("/kernel/dpl/clock");
const debug_log  = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7  = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71 = mpu_armv7.addInstance();
const mpu_armv72 = mpu_armv7.addInstance();
const mpu_armv73 = mpu_armv7.addInstance();
const mpu_armv74 = mpu_armv7.addInstance();
const mpu_armv75 = mpu_armv7.addInstance();

/**
 * Write custom configuration values to the imported modules.
 */
flash1.$name                            = "CONFIG_FLASH0";
flash1.device                           = "CUSTOM_FLASH";
flash1.cmdBlockErase3B                  = "0xD8";
flash1.cmdSectorErase3B                 = "0x20";
flash1.dummyClksCmd                     = 0;
flash1.proto_isAddrReg                  = false;
flash1.strDtr_isAddrReg                 = false;
flash1.cmdExtType                       = "NONE";
flash1.xspiWipReg                       = "0x00000000";
flash1.idNumBytes                       = 5;
flash1.flashDeviceBusyTimeout           = 40000000;
flash1.flashPageProgTimeout             = 120;
flash1.dataLines                        = "4";
flash1.dummy_isAddrReg                  = false;
flash1.quirks                           = "NULL";
flash1.fname                            = "MT25QU128ABAE12";
flash1.fourByteEnableSeq                = "0xB7";
flash1.enable4BAddr                     = false;
flash1.deviceBusyType                   = "0";
flash1.xspiWipRdCmd                     = "0x00";
flash1.flashSize                        = 16777216;
flash1.flashManfId                      = "0x20";
flash1.flashDeviceId                    = "0xBB18";
flash1.flashBlockSize                   = 65536;
flash1.cmdBlockErase4B                  = "0xFF";
flash1.cmdSectorErase4B                 = "0xFF";
flash1.resetType                        = "0x3D";
flash1.addressByteSupport               = "0";
flash1.srWel                            = 0;
flash1.proto_cmdRegRd                   = "0x00";
flash1.proto_cmdRegWr                   = "0x00";
flash1.proto_cfgReg                     = "0x00000000";
flash1.proto_mask                       = "0x00";
flash1.proto_bitP                       = 0;
flash1.dummy_cmdRegRd                   = "0x00";
flash1.dummy_cmdRegWr                   = "0x00";
flash1.dummy_cfgReg                     = "0x00000000";
flash1.dummy_mask                       = "0x00";
flash1.dummy_bitP                       = 0;
flash1.strDtr_cmdRegRd                  = "0x00";
flash1.strDtr_cmdRegWr                  = "0x00";
flash1.strDtr_cfgReg                    = "0x00000000";
flash1.strDtr_shift                     = 0;
flash1.strDtr_mask                      = "0x00";
flash1.strDtr_bitP                      = 0;
flash1.protocol                         = "1s_1s_4s";
flash1.cmdRd                            = "0x6B";
flash1.dummyClksRd                      = 8;
flash1.cmdWr                            = "0x32";
flash1.flash444Seq                      = "0";
flash1.peripheralDriver.$name           = "CONFIG_OSPI0";
flash1.peripheralDriver.chipSelect      = "CS1";
flash1.peripheralDriver.dataLines       = "4";
flash1.peripheralDriver.dmaEnable       = true;
flash1.peripheralDriver.inputClkFreq    = 200000000;
flash1.peripheralDriver.OSPI.CLK.pu_pd  = "pu";
flash1.peripheralDriver.OSPI.DQS.$used  = false;
flash1.peripheralDriver.OSPI.D7.rx      = false;
flash1.peripheralDriver.OSPI.D7.$used   = false;
flash1.peripheralDriver.OSPI.D6.$used   = false;
flash1.peripheralDriver.OSPI.D5.$used   = false;
flash1.peripheralDriver.OSPI.D4.$used   = false;
flash1.peripheralDriver.OSPI.D3.pu_pd   = "pu";
flash1.peripheralDriver.OSPI.D2.pu_pd   = "pu";
flash1.peripheralDriver.OSPI.D1.pu_pd   = "pu";
flash1.peripheralDriver.OSPI.D0.pu_pd   = "pu";
flash1.peripheralDriver.OSPI.CSn1.pu_pd = "pu";

ddr1.$name                    = "CONFIG_DDR0";
ddr1.ddrConfigIncludeFileName = "dev2_board_ddrReginit.h";

udma1.$name                        = "CONFIG_UDMA0";
flash1.peripheralDriver.udmaDriver = udma1;

clock.timerInputClkHz = 250000000;

debug_log.enableUartLog        = true;
debug_log.uartLog.$name        = "CONFIG_UART_LOG";
debug_log.uartLog.UART.$assign = "USART0";

mpu_armv71.$name             = "CONFIG_MPU_REGION0";
mpu_armv71.size              = 31;
mpu_armv71.attributes        = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute      = false;

mpu_armv72.$name             = "CONFIG_MPU_REGION1";
mpu_armv72.size              = 15;
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv73.$name             = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr          = 0x41010000;
mpu_armv73.size              = 15;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv74.$name             = "CONFIG_MPU_REGION3";
mpu_armv74.baseAddr          = 0x70000000;
mpu_armv74.size              = 21;
mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv75.$name    = "CONFIG_MPU_REGION5";
mpu_armv75.baseAddr = 0x80000000;
mpu_armv75.size     = 31;

/**
 * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
 * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
 * re-solve from scratch.
 */
flash1.peripheralDriver.OSPI.$suggestSolution      = "OSPI0";
flash1.peripheralDriver.OSPI.CLK.$suggestSolution  = "OSPI0_CLK";
flash1.peripheralDriver.OSPI.D3.$suggestSolution   = "OSPI0_D3";
flash1.peripheralDriver.OSPI.D2.$suggestSolution   = "OSPI0_D2";
flash1.peripheralDriver.OSPI.D1.$suggestSolution   = "OSPI0_D1";
flash1.peripheralDriver.OSPI.D0.$suggestSolution   = "OSPI0_D0";
flash1.peripheralDriver.OSPI.CSn1.$suggestSolution = "OSPI0_CSn1";
debug_log.uartLog.UART.RXD.$suggestSolution        = "UART0_RXD";
debug_log.uartLog.UART.TXD.$suggestSolution        = "UART0_TXD";

Turning DMA on the flash still results in the same issue if DDR is enabled, but it works without DDR and DMA enabled.  If Phy mode is enabled, it gets stuck at the dummyCycle set: 

Here is the sysconfig for the uart_uniflash:

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM243x@08.06.00"
 * @versions {"tool":"1.17.0+3128"}
 */

/**
 * Import the modules used in this configuration.
 */
const flash       = scripting.addModule("/board/flash/flash", {}, false);
const flash1      = flash.addInstance();
const bootloader  = scripting.addModule("/drivers/bootloader/bootloader", {}, false);
const bootloader1 = bootloader.addInstance();
const mmcsd       = scripting.addModule("/drivers/mmcsd/mmcsd", {}, false);
const mmcsd1      = mmcsd.addInstance();
const uart        = scripting.addModule("/drivers/uart/uart", {}, false);
const uart1       = uart.addInstance();
const udma        = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1       = udma.addInstance();
const clock       = scripting.addModule("/kernel/dpl/clock");
const debug_log   = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7   = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71  = mpu_armv7.addInstance();
const mpu_armv72  = mpu_armv7.addInstance();
const mpu_armv73  = mpu_armv7.addInstance();
const mpu_armv74  = mpu_armv7.addInstance();
const mpu_armv75  = mpu_armv7.addInstance();

/**
 * Write custom configuration values to the imported modules.
 */
flash1.$name                            = "CONFIG_FLASH0";
flash1.device                           = "CUSTOM_FLASH";
flash1.cmdBlockErase3B                  = "0xD8";
flash1.cmdSectorErase3B                 = "0x20";
flash1.dummyClksCmd                     = 0;
flash1.proto_isAddrReg                  = false;
flash1.strDtr_isAddrReg                 = false;
flash1.cmdExtType                       = "NONE";
flash1.xspiWipReg                       = "0x00000000";
flash1.idNumBytes                       = 5;
flash1.flashDeviceBusyTimeout           = 40000000;
flash1.flashPageProgTimeout             = 120;
flash1.dataLines                        = "4";
flash1.flashSize                        = 16777216;
flash1.flashManfId                      = "0x20";
flash1.flashDeviceId                    = "0xBB18";
flash1.flashBlockSize                   = 65536;
flash1.cmdBlockErase4B                  = "0xFF";
flash1.cmdSectorErase4B                 = "0xFF";
flash1.resetType                        = "0x3D";
flash1.dummy_isAddrReg                  = false;
flash1.quirks                           = "NULL";
flash1.fname                            = "MT25QU128ABAE12";
flash1.fourByteEnableSeq                = "0xB7";
flash1.enable4BAddr                     = false;
flash1.addressByteSupport               = "0";
flash1.protocol                         = "1s_1s_4s";
flash1.cmdRd                            = "0x6B";
flash1.deviceBusyType                   = "0";
flash1.xspiWipRdCmd                     = "0x05";
flash1.cmdWr                            = "0x32";
flash1.dummyClksRd                      = 8;
flash1.flash444Seq                      = "00000";
flash1.peripheralDriver.$name           = "CONFIG_OSPI0";
flash1.peripheralDriver.chipSelect      = "CS1";
flash1.peripheralDriver.dataLines       = "4";
flash1.peripheralDriver.dmaEnable       = true;
flash1.peripheralDriver.inputClkFreq    = 200000000;
flash1.peripheralDriver.OSPI.CLK.pu_pd  = "pu";
flash1.peripheralDriver.OSPI.DQS.$used  = false;
flash1.peripheralDriver.OSPI.D7.rx      = false;
flash1.peripheralDriver.OSPI.D7.$used   = false;
flash1.peripheralDriver.OSPI.D6.$used   = false;
flash1.peripheralDriver.OSPI.D5.$used   = false;
flash1.peripheralDriver.OSPI.D4.$used   = false;
flash1.peripheralDriver.OSPI.D3.pu_pd   = "pu";
flash1.peripheralDriver.OSPI.D2.pu_pd   = "pu";
flash1.peripheralDriver.OSPI.D1.pu_pd   = "pu";
flash1.peripheralDriver.OSPI.D0.pu_pd   = "pu";
flash1.peripheralDriver.OSPI.CSn1.pu_pd = "pu";

bootloader1.$name     = "CONFIG_BOOTLOADER0";
bootloader1.bootMedia = "MEM";

mmcsd1.$name        = "CONFIG_MMCSD0";
mmcsd1.moduleSelect = "MMC0";
mmcsd1.cardType     = "NO_DEVICE";
mmcsd1.inputClkFreq = 250000000;

uart1.$name            = "CONFIG_UART0";
uart1.intrEnable       = "DISABLE";
uart1.inputClkFreq     = 96000000;
uart1.UART.$assign     = "USART0";
uart1.UART.RXD.$assign = "UART0_RXD";
uart1.UART.TXD.$assign = "UART0_TXD";

udma1.$name                        = "CONFIG_UDMA0";
flash1.peripheralDriver.udmaDriver = udma1;

debug_log.enableCssLog = false;

mpu_armv71.$name             = "CONFIG_MPU_REGION0";
mpu_armv71.size              = 31;
mpu_armv71.attributes        = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute      = false;

mpu_armv72.$name             = "CONFIG_MPU_REGION1";
mpu_armv72.size              = 15;
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv73.$name             = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr          = 0x41010000;
mpu_armv73.size              = 15;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv74.$name             = "CONFIG_MPU_REGION3";
mpu_armv74.baseAddr          = 0x70000000;
mpu_armv74.size              = 21;
mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv75.$name    = "CONFIG_MPU_REGION5";
mpu_armv75.baseAddr = 0x80000000;
mpu_armv75.size     = 31;

/**
 * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
 * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
 * re-solve from scratch.
 */
flash1.peripheralDriver.OSPI.$suggestSolution      = "OSPI0";
flash1.peripheralDriver.OSPI.CLK.$suggestSolution  = "OSPI0_CLK";
flash1.peripheralDriver.OSPI.D3.$suggestSolution   = "OSPI0_D3";
flash1.peripheralDriver.OSPI.D2.$suggestSolution   = "OSPI0_D2";
flash1.peripheralDriver.OSPI.D1.$suggestSolution   = "OSPI0_D1";
flash1.peripheralDriver.OSPI.D0.$suggestSolution   = "OSPI0_D0";
flash1.peripheralDriver.OSPI.CSn1.$suggestSolution = "OSPI0_CSn1";
mmcsd1.MMC0.$suggestSolution                       = "MMC0";

Which results in the following output if ddr is not enabled:

 If DDR is enabled:

Hi Jacob,

My apologies, I got confused between DDR the memory and the DDR mode of operation in OSPI/QSPI protocols. I think there is a debug call setup for today, we can look into it. 

Regards,
Anand Mahadevan SS

Hello, in reply to what we talked about in the call, I will provide scoped data, clock and cs lines for the dummy cycle write. I will not be able to before tomorrow, as I need to coordinate with the hardware developers.

I have captured files that can be used to see what the spi lines and clock and chip select are. This happens when running the ospi_flash_io project, configured for qspi as we had talked about over the phone. When DDR is configured, we couldn't figure out what command it's trying to do. It should be doing a read of the vendor ID, that's 0x9F command without ddr config. But instead it's doing 0x30 which is not a valid command and not driving chip select.

Also just a note that UART Uniflash over ospi (with ddr configured) works fine.

Jacob, 

As discussed we have taken this debug and discussion offline. We can continue there, I believe it is okay to close this thread for now. Let me know if there is anything else you would like to clarify in this forum itself.

Regards,
Anand Mahadevan SS

I think it makes no sense to close this one until that the issue is not resolved. 

Christophe,

While we received the Molex board a few days back, but had trouble finding the right debugger. We have the setup ready now. We will try to reproduce the issue at our end and get back with updates in 2 days.

Regards,
Anand Mahadevan SS

Anand,

Thanks a lot for the feedback. 

Thanks

Christophe.

Christophe,

We are able to reproduce the issue, and Daviel is following up on further steps to find out what part of the DDR configuration is throwing off the QSPI flash setup. We will get back to you in another 2 days.

Regards,
Anand Mahadevan SS

Christophe,

Our conjecture is that during a particular stage in the DDR initialization, it throws off the flash configuration and we are unable to communicate to the flash. Daviel is currently looking to the details of this. Will provide more details by next week. Let me know if there are any other concerns or observations.

Regards,
Anand Mahadevan SS

Anand,

Thanks for the feedback.

It is clear to me that you have understood the root cause. Which is a good first step. But, have you planned to fix it? Do you have some timeline to share with us? 

Thanks

Christophe. 

I believe I identified the root of the issue for why you cannot read the QSPI flash. During init_DDR, a function enables VTT; the pin used for this is CS1. But we can skip this function since VTT is not needed for LPDDR. Here is my modified DDR.c file, please use this in your build as we implement a fix for the next SDK. The line I modified is 450-454. Can you test this and follow up on your results?

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 *  are met:
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 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 *****************************************************************************/

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include <stdint.h>
#include <string.h>
#include <kernel/dpl/DebugP.h>
#include <drivers/hw_include/hw_types.h>
#include <drivers/soc.h>
#include <drivers/ddr.h>
#include <drivers/ddr/v0/cdn_drv.h>
#include <drivers/ddr/v0/csl_emif.h>
#include <kernel/dpl/ClockP.h>
#include <kernel/dpl/CacheP.h>

#if defined (SOC_AM64X) || defined (SOC_AM243X)
#include <drivers/ddr/v0/soc/am64x_am243x/ddr_soc.h>
#endif

/* ========================================================================== */
/*                             Macros & Typedefs                              */
/* ========================================================================== */

#define DDR_CTL_REG_OFFSET              (0)
#define DDR_SRAM_MAX                    (512U)
#define DDR_TYPE_MASK                   (0xF00U)
#define DDR4_MEMORY                     (0xA00U)
#define LPDDR4_MEMORY                   (0xB00U)
/*FSP MAIN_CTRL_MMR register offsets*/
/* LPDDR4 FSP Clock Change Request Register - DDR Controller to request the DDR PLL clock frequency change (read only)*/
#define DDR_FSP_CLKCHNG_REQ    0x14080U
/* LPDDR4 FSP Clock Change Acknowledge Register - acknowledge a DDR PLL clock frequency change to the DDR Controller (r/w) */
#define DDR_FSP_CLKCHNG_ACK    0x140C0U

#define DDR_CTL_REG_BASE        0x0F308000U
#define DDR_PI_REG_BLOCK_OFFS   0x2000U
#define DDR_PI_0_SFR_OFFS       0x0U
#define DDR_CTL_0_SFR_OFFS      0x0U
#define DDR_PI_83_SFR_OFFS      0x14CU
#define DDR_CTL_342_SFR_OFFS    0x558U
/* Trigger Start bit*/
#define TRIGGER_START_BIT        0x00000B01U

#define KEY0                    0x68EF3490U
#define KEY1                    0xD172BC5AU

#define DDR_REQ_TYPE_0    0
#define DDR_REQ_TYPE_1    1
#define DDR_REQ_TYPE_2    2

/* ========================================================================== */
/*                 Internal Function Declarations                             */
/* ========================================================================== */


/* ========================================================================== */
/*                         Global Variables Declarations                      */
/* ========================================================================== */

static LPDDR4_Config gLpddrCfg;
static LPDDR4_PrivateData gLpddrPd;

/* ========================================================================== */
/*                         Extern Function declerations                       */
/* ========================================================================== */
extern void DDR_socEnableVttRegulator(void);

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */
static void DDR_setFreq(uint64_t freq)
{
    uint32_t module = TISCI_DEV_DDR16SS0;
    uint32_t clock = TISCI_DEV_DDR16SS0_DDRSS_DDR_PLL_CLK;
    int32_t status = SystemP_SUCCESS;

    status = SOC_moduleSetClockFrequency(module, clock, freq);
    if(status != SystemP_SUCCESS)
    {
        DebugP_logError("SOC_moduleSetClockFrequency failed !!!\n");
    }
}

static void DDR_changeFreqAck(DDR_Params *prms)
{
    uint32_t req, req_type, counter;

    /*unlock MMR reg 5*/
    /*Partition5 lockkey0*/
    HW_WR_REG32((CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK5_KICK0), KEY0);
    /*Partition5 lockkey1*/
    HW_WR_REG32(( CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK5_KICK1), KEY1);

    ClockP_usleep(500);

    for(counter = 0; counter < prms->fshcount; counter++)
    {
        req = (HW_RD_REG32(CSL_CTRL_MMR0_CFG0_BASE + DDR_FSP_CLKCHNG_REQ) & 0x80);
        while((req ) == 0x0)
        {
            req = (HW_RD_REG32(CSL_CTRL_MMR0_CFG0_BASE + DDR_FSP_CLKCHNG_REQ) & 0x80);
        }

        req_type = HW_RD_REG32(CSL_CTRL_MMR0_CFG0_BASE + DDR_FSP_CLKCHNG_REQ) & 0x03;

        if(req_type == DDR_REQ_TYPE_1)
        {
            DDR_setFreq(prms->clk1Freq);
        }
        else if(req_type == DDR_REQ_TYPE_2)
        {
            DDR_setFreq(prms->clk2Freq);
        }
        else if(req_type == DDR_REQ_TYPE_0)
        {
            DDR_setFreq(25000000);
        }

        /*set the ack bit*/
        HW_WR_REG32((CSL_CTRL_MMR0_CFG0_BASE + DDR_FSP_CLKCHNG_ACK), 0x1);
        while(((HW_RD_REG32((CSL_CTRL_MMR0_CFG0_BASE + DDR_FSP_CLKCHNG_REQ))) & 0x80) == 0x80);
        /*clear the ack bit */
        HW_WR_REG32((CSL_CTRL_MMR0_CFG0_BASE + DDR_FSP_CLKCHNG_ACK), 0x0);
    }
}

static int32_t DDR_setClock(DDR_Params *prms)
{
    int32_t status = SystemP_SUCCESS;

    if((HW_RD_REG32(DDR_CTL_REG_BASE) & DDR_TYPE_MASK) == DDR4_MEMORY)
    {
        /* Type is DDR4*/
        DDR_setFreq(prms->clk1Freq);
    }
    else
    {
        /* Type is LPDDR4. Start Frequency handshake.*/
        DDR_setFreq(25000000);

        ClockP_usleep(5000);

        /*trigger the start bit (from PI)*/
        HW_WR_REG32(DDR_CTL_REG_BASE + DDR_PI_REG_BLOCK_OFFS + DDR_PI_0_SFR_OFFS,   TRIGGER_START_BIT);

        ClockP_usleep(500);

        /*trigger the start bit (from CTL)*/
        HW_WR_REG32(DDR_CTL_REG_BASE + DDR_CTL_0_SFR_OFFS,   TRIGGER_START_BIT);

        ClockP_usleep(1000);

        DDR_changeFreqAck(prms);

        ClockP_usleep(500);

        /*PI INT STATUS*/
        while(((HW_RD_REG32(DDR_CTL_REG_BASE + DDR_PI_REG_BLOCK_OFFS + DDR_PI_83_SFR_OFFS)) & 0x1) != 0x1);
        /*CTL_342[25] = int status init[1] = 1 - The MC initialization has been completed.*/
        while((HW_RD_REG32(DDR_CTL_REG_BASE + DDR_CTL_342_SFR_OFFS)&0x02000000)!= 0x02000000);
    }

    return status;
}

static int32_t DDR_probe(void)
{
    uint32_t status = 0U;
    uint16_t configsize = 0U;
    int32_t ret = SystemP_SUCCESS;

    status = LPDDR4_Probe(&gLpddrCfg, &configsize);
    if ((status != 0) || (configsize != sizeof(LPDDR4_PrivateData)) ||
        (configsize > DDR_SRAM_MAX))
    {
        DebugP_logError("DDR4/LPDDR4_Probe failed !!!\n");
        ret = SystemP_FAILURE;
    }

    return ret;
}

static int32_t DDR_initDrv(void)
{
    uint32_t status = 0U;
    int32_t ret = SystemP_SUCCESS;

    if ((sizeof(gLpddrPd) != sizeof(LPDDR4_PrivateData)) ||
        (sizeof(gLpddrPd) > DDR_SRAM_MAX))
    {
        DebugP_logError("Invalid parameters !!!\n");
        ret = SystemP_FAILURE;
    }

    if(ret == SystemP_SUCCESS)
    {
        gLpddrCfg.ctlBase = (struct LPDDR4_CtlRegs_s *)CSL_DDR16SS0_CTL_CFG_BASE;
        gLpddrCfg.infoHandler = NULL;

        status = LPDDR4_Init(&gLpddrPd, &gLpddrCfg);
        if ((status > 0U) ||
            (gLpddrPd.ctlBase != (struct LPDDR4_CtlRegs_s *)gLpddrCfg.ctlBase) ||
            (gLpddrPd.ctlInterruptHandler != gLpddrCfg.ctlInterruptHandler) ||
            (gLpddrPd.phyIndepInterruptHandler != gLpddrCfg.phyIndepInterruptHandler))
        {
            DebugP_logError("DDR4/LPDDR4_Init failed !!!\n");
            ret = SystemP_FAILURE;
        }
    }

    return ret;
}

static int32_t DDR_initHwRegs(DDR_Params *prms)
{
    uint32_t status = 0U;
    int32_t ret = SystemP_SUCCESS;

    status = LPDDR4_WriteCtlConfig(&gLpddrPd,
                                    prms->ddrssCtlReg,
                                    prms->ddrssCtlRegNum,
                                    prms->ddrssCtlRegCount);
    if (status == SystemP_SUCCESS)
    {
        status = LPDDR4_WritePhyIndepConfig(&gLpddrPd,
                                            prms->ddrssPhyIndepReg,
                                            prms->ddrssPhyIndepRegNum,
                                            prms->ddrssPhyIndepRegCount);
    }
    if (status == SystemP_SUCCESS)
    {
        status = LPDDR4_WritePhyConfig(&gLpddrPd,
                                        prms->ddrssPhyReg,
                                        prms->ddrssPhyRegNum,
                                        prms->ddrssPhyRegCount);
    }

    if (status != SystemP_SUCCESS)
    {
        DebugP_logError("DDR config write failed !!!\r\n");
        ret = SystemP_FAILURE;
    }
    return ret;
}

static int32_t DDR_start(void)
{
    uint32_t status = 0U;
    uint32_t regval = 0U;
    uint32_t offset = 0U;
    int32_t ret = SystemP_SUCCESS;

    offset = DDR_CTL_REG_OFFSET;

    status = LPDDR4_ReadReg(&gLpddrPd, LPDDR4_CTL_REGS, offset, &regval);

    if((HW_RD_REG32(DDR_CTL_REG_BASE) & DDR_TYPE_MASK) == DDR4_MEMORY)
    {
        /* DDR4 memory */
        if ((status > 0U) || ((regval & 0x1U) != 0U))
        {
            DebugP_logError("DDR4_ReadReg failed !!!\r\n");
            ret = SystemP_FAILURE;
        }
    }
    else
    {
        /* LPDDR4 memory */
        if ((status > 0U) || ((regval & 0x1U) != 1U))
        {
            DebugP_logError("LPDDR4_ReadReg failed !!!\r\n");
            ret = SystemP_FAILURE;
        }
    }

    if(ret == SystemP_SUCCESS)
    {
        status = LPDDR4_Start(&gLpddrPd);
        if (status > 0U)
        {
            DebugP_logError("DDR4/LPDDR4_Start failed !!!\r\n");
            ret = SystemP_FAILURE;
        }

        if(ret == SystemP_SUCCESS)
        {
            status = LPDDR4_ReadReg(&gLpddrPd, LPDDR4_CTL_REGS, offset, &regval);
            if ((status > 0U) || ((regval & 0x1U) != 1U))
            {
                DebugP_logError("DDR4/LPDDR4_ReadReg failed !!!\r\n");
                ret = SystemP_FAILURE;
            }
        }
    }

    return ret;
}

static uint32_t DDR_isEnabled (DDR_Params *prm)
{
    uint32_t isEnabled = 0;
    struct LPDDR4_CtlRegs_s * ctlRegBase = (struct LPDDR4_CtlRegs_s *)gLpddrCfg.ctlBase;

    if ((HW_RD_REG32(&(ctlRegBase->LPDDR4__PI_START__REG)) & 0x1) &&
            (HW_RD_REG32(&(ctlRegBase->LPDDR4__START__REG)) & 0x1))
    {
        isEnabled = 1;
    }

    return isEnabled;
}

static int32_t DDR_inlineECCCfg (DDR_Params *prm)
{
    int32_t status = SystemP_SUCCESS;

    if (prm->eccRegion != NULL)
    {
        /* Disable inline ECC */
        DDR_enableInlineECC (0U);

        CSL_EmifConfig emifCfg;
        uintptr_t      memPtr;
        memset(&emifCfg, 0, sizeof(emifCfg));

        emifCfg.bEnableMemoryECC = TRUE;
        emifCfg.bReadModifyWriteEnable = TRUE;
        emifCfg.bECCCheck = TRUE;
        emifCfg.bWriteAlloc = TRUE;
        emifCfg.ECCThreshold = 1U;

        emifCfg.pMemEccCfg.startAddr[0] = prm->eccRegion->ddrEccStart0;
        emifCfg.pMemEccCfg.endAddr[0] = prm->eccRegion->ddrEccEnd0;
        emifCfg.pMemEccCfg.startAddr[1] = prm->eccRegion->ddrEccStart1;
        emifCfg.pMemEccCfg.endAddr[1] = prm->eccRegion->ddrEccEnd1;
        emifCfg.pMemEccCfg.startAddr[2] = prm->eccRegion->ddrEccStart2;
        emifCfg.pMemEccCfg.endAddr[2] = prm->eccRegion->ddrEccEnd2;

        status = CSL_emifConfig((CSL_emif_sscfgRegs *)CSL_DDR16SS0_SS_CFG_BASE,
                            &emifCfg);

        if (status == SystemP_SUCCESS)
        {
            /* Prime memory section 1 with known pattern */
            if (prm->eccRegion->ddrEccStart0 < prm->eccRegion->ddrEccEnd0)
            {
                for (memPtr = prm->eccRegion->ddrEccStart0;
                        memPtr < prm->eccRegion->ddrEccEnd0; memPtr += 4)
                {
                    *((uint32_t *) (memPtr + DDR_DRAM_START_ADDR)) = memPtr + DDR_DRAM_START_ADDR;
                }

                CacheP_wbInv((void *)(prm->eccRegion->ddrEccStart0 + DDR_DRAM_START_ADDR),
                    prm->eccRegion->ddrEccEnd0 - prm->eccRegion->ddrEccStart0,
                                                            CacheP_TYPE_ALL);
            }

            /* Prime memory section 2 with known pattern */
            if (prm->eccRegion->ddrEccStart1 < prm->eccRegion->ddrEccEnd1)
            {
                for (memPtr = prm->eccRegion->ddrEccStart1;
                        memPtr < prm->eccRegion->ddrEccEnd1; memPtr += 4)
                {
                    *((uint32_t *) (memPtr + DDR_DRAM_START_ADDR)) = memPtr + DDR_DRAM_START_ADDR;
                }

                CacheP_wbInv((void *)(prm->eccRegion->ddrEccStart1 + DDR_DRAM_START_ADDR),
                    prm->eccRegion->ddrEccEnd1 - prm->eccRegion->ddrEccStart1,
                                                            CacheP_TYPE_ALL);
            }

            /* Prime memory section 3 with known pattern */
            if (prm->eccRegion->ddrEccStart2 < prm->eccRegion->ddrEccEnd2)
            {
                for (memPtr = prm->eccRegion->ddrEccStart2;
                        memPtr < prm->eccRegion->ddrEccEnd2; memPtr += 4)
                {
                    *((uint32_t *) (memPtr + DDR_DRAM_START_ADDR)) = memPtr + DDR_DRAM_START_ADDR;
                }

                CacheP_wbInv((void *)(prm->eccRegion->ddrEccStart2 + DDR_DRAM_START_ADDR),
                    prm->eccRegion->ddrEccEnd2 - prm->eccRegion->ddrEccStart2,
                                                            CacheP_TYPE_ALL);
            }
        }

        if (status == SystemP_SUCCESS)
        {
            status = CSL_emifClearECCInterruptStatus((CSL_emif_sscfgRegs *)CSL_DDR16SS0_SS_CFG_BASE,
                                                    CSL_EMIF_SSCFG_V2A_INT_SET_REG_ECC1BERR_EN_MASK
                                                    | CSL_EMIF_SSCFG_V2A_INT_SET_REG_ECCM1BERR_EN_MASK
                                                    | CSL_EMIF_SSCFG_V2A_INT_SET_REG_ECC2BERR_EN_MASK);

            if (status == SystemP_SUCCESS)
            {
                status = CSL_emifEnableECCInterrupts((CSL_emif_sscfgRegs *)CSL_DDR16SS0_SS_CFG_BASE,
                                                    CSL_EMIF_SSCFG_V2A_INT_SET_REG_ECC1BERR_EN_MASK
                                                    | CSL_EMIF_SSCFG_V2A_INT_SET_REG_ECCM1BERR_EN_MASK
                                                    | CSL_EMIF_SSCFG_V2A_INT_SET_REG_ECC2BERR_EN_MASK);
            }
        }

        DDR_enableInlineECC (1U);
    }
    else
    {
        status = SystemP_FAILURE;
    }

    return status;
}

int32_t DDR_init(DDR_Params *prm)
{
    uint32_t isEnabled = 0;
    int32_t status = SystemP_SUCCESS;
    int32_t isLPDDR = 1;

    if (isLPDDR == 0){
        DDR_socEnableVttRegulator();
    }

    /* power and clock to DDR and EMIF is done form outside using SysConfig */

    /* Configure MSMC2DDR Bridge Control register. Configure REGION_IDX, SDRAM_IDX and SDRAM_3QT.*/
    HW_WR_REG32((CSL_DDR16SS0_SS_CFG_BASE + 0x20), 0x1EF);

    /* Configure DDRSS_ECC_CTRL_REG register. Disable ECC. */
    HW_WR_REG32((CSL_DDR16SS0_SS_CFG_BASE + 0x120), 0x00);

    status = DDR_probe();
    if(status == SystemP_SUCCESS)
    {
        status = DDR_initDrv();
    }
    isEnabled = DDR_isEnabled(prm);
    if (!isEnabled)
    {
        if(status == SystemP_SUCCESS)
        {
            status = DDR_initHwRegs(prm);
        }
        if(status == SystemP_SUCCESS)
        {
            status = DDR_setClock(prm);
        }
        if(status == SystemP_SUCCESS)
        {
            status = DDR_start();
        }
    }

    if (status == SystemP_SUCCESS)
    {
        if (prm->enableEccFlag)
        {
            status = DDR_inlineECCCfg (prm);
        }
    }

    return status;
}


void DDR_Params_init(DDR_Params *prms)
{
    memset((void*)prms, 0, sizeof(DDR_Params));
}

void DDR_enableInlineECC (uint8_t enableFlag)
{
    if (1U == enableFlag)
    {
        CSL_emifEnableECC ((CSL_emif_sscfgRegs *)CSL_DDR16SS0_SS_CFG_BASE);
    }
    else
    {
        /* Disable inline ECC */
        CSL_emifDisableECC ((CSL_emif_sscfgRegs *)CSL_DDR16SS0_SS_CFG_BASE);
    }
}

int32_t DDR_clearECCError (uint8_t errorType)
{
    int32_t status = SystemP_SUCCESS;

    if (DDR_ECC_1B_ERROR == errorType)
    {
        /* Clear Specific ECC error */
        status = CSL_emifClearECCError((CSL_emif_sscfgRegs *)CSL_DDR16SS0_SS_CFG_BASE,
                                           CSL_EMIF_ECC_ERROR_TYPE_SINGLE_BIT);

        if (status == SystemP_SUCCESS)
        {
            /* Clear ECC interrupt bits */
            status = CSL_emifClearECCInterruptStatus((CSL_emif_sscfgRegs *)CSL_DDR16SS0_SS_CFG_BASE,
                                                CSL_EMIF_SSCFG_V2A_INT_SET_REG_ECC1BERR_EN_MASK
                                                | CSL_EMIF_SSCFG_V2A_INT_SET_REG_ECCM1BERR_EN_MASK);
        }
    }
    else if (DDR_ECC_2B_ERROR == errorType)
    {
        /* Clear specific error */
        status = CSL_emifClearECCError((CSL_emif_sscfgRegs *)CSL_DDR16SS0_SS_CFG_BASE,
                                           CSL_EMIF_ECC_ERROR_TYPE_DOUBLE_BIT);

        if (status == SystemP_SUCCESS)
        {
            /* Clear ECC interrupt bits */
            status = CSL_emifClearECCInterruptStatus((CSL_emif_sscfgRegs *)CSL_DDR16SS0_SS_CFG_BASE,
                                                     CSL_EMIF_SSCFG_V2A_INT_SET_REG_ECC2BERR_EN_MASK);
        }
    }
    else
    {
        /* Clear all errors */
        status = CSL_emifClearAllECCErrors ((CSL_emif_sscfgRegs *)CSL_DDR16SS0_SS_CFG_BASE);

        if (status == SystemP_SUCCESS)
        {
            status = CSL_emifClearECCInterruptStatus((CSL_emif_sscfgRegs *)CSL_DDR16SS0_SS_CFG_BASE,
                                                CSL_EMIF_SSCFG_V2A_INT_SET_REG_ECC1BERR_EN_MASK
                                                | CSL_EMIF_SSCFG_V2A_INT_SET_REG_ECCM1BERR_EN_MASK
                                                | CSL_EMIF_SSCFG_V2A_INT_SET_REG_ECC2BERR_EN_MASK);
        }
    }

    return status;
}

int32_t DDR_getECCErrorInfo (DDR_ECCErrorInfo *ECCErrorInfo)
{
    int32_t status = SystemP_SUCCESS;
    CSL_ECCErrorInfo csl_ECCErrorInfo = {0};

    if (ECCErrorInfo != NULL)
    {
        status = CSL_emifGetECCErrorInfo ((CSL_emif_sscfgRegs *)CSL_DDR16SS0_SS_CFG_BASE, &csl_ECCErrorInfo);

        memcpy ((void *)ECCErrorInfo, (void *)&csl_ECCErrorInfo, sizeof(csl_ECCErrorInfo));
    }
    else
    {
        status = SystemP_FAILURE;
    }

    return status;
}