• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 30 subscribers
  • Views 618 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS570LS1227: Clarification on eQEP Position Counter Reset on Index Event mode and PCU and PCO flags applicability

TMS570LS1227: Fixing eQEP QCTMR reset event

Luis Lanca
Prodigy 250 points
Part Number: TMS570LS1227
Other Parts Discussed in Thread: HALCOGEN

Dear All,

How do you I configure the eQEP module edge capture unit to achieve the capture timer reset behaviour as described in SPNU515C–March 2018, page 903, sec 21.5 eQEP Edge Capture Unit?

"The eQEP capture timer (QCTMR) runs from prescaled VCLK4 and the prescaler is programmed by the
QCAPCTL[CCPS] bits. The capture timer (QCTMR) value is latched into the capture period register
(QCPRD) on every unit position event and then the capture timer is reset, a flag is set in
QEPSTS:UPEVNT to indicate that new value is latched into the QCPRD register. Software can check this
status flag before reading the period register for low speed measurement and clear the flag by writing 1."

Our configuration is not working are expected, i.e., reset of QCTMR happen on every position event.

Current configuration code for the capture timer sets the memory mapped register QCAPCTL bits in the following sequential order :

  1. Write 1 to bit QCAPCTL[15] (enable capture unit)
  2. Write 0 to bits QCAPCTL[5..6] (= CAPCLK = VCLK4/2)
  3. Write 1 to bit QCAPCTL[4] (= CAPCLK = VCLK4/2)
  4. Write 0 to bits QCAPCTL[0..3] (= UPEVNT = QCLK/1)

Thanks for your time and support.

With my best regards,

Luis

  • 0
    TI__Guru 69771 points

    Hi Luis,

    We started working on your issue and will try to provide an update ASAP.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 250 points

    Hello Jagdish, 

    Thanks for the support!

    In addition to my original question, I would like to know in general for any memory mapped register if there is a recommend procedure clear/set bits e.g,

    - should the configuration of any used eqep control register (clear/set bits) only be done in one go?

    - control register bits not used should be explicitly sets to the reset values documented in the technical reference manual? 

    Best regards, 

    Luís 

  • 0 in reply to jagadish gundavarapu
    Prodigy 250 points

    Hello Jagadish, 

    I am writing this message to kindly ask if you got any updates on the matter. 

    Thanks for the time and support. 

    Best regards, 

    Luis

  • 0 in reply to Luis Lanca
    TI__Guru 69771 points

    Hi Luis,

    My apologies for the late reply.

    Is it possible for you to attach your complete project, so that i can easily debug the issue at my end.

    Luis Lanca said:
    In addition to my original question, I would like to know in general for any memory mapped register if there is a recommend procedure clear/set bits

    To SET n'th bit in the register:
    REG |= (1 << n);

    To CLEAR n'th bit in the register:
    REG &= ~(1 << x);

    --

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 250 points

    Hello Jagadish, 

    Thanks for your answer, clearing and setting individual bits is aligned to our understanding. 

     We are not using TI CCS, sharing a project is therefore difficult. 

    It would be really helpful if you could answer the following related questions:

    - should the configuration of any used eqep control register (clear/set bits) only be done in one go? 

    - control register bits not used should be explicitly sets to the reset values documented in the reference manual?

    - we want to reset of QCTMR on every position event.The Current configuration code for the capture timer sets the memory mapped register QCAPCTL bits in the following sequential order :

    1. Write 1 to bit QCAPCTL[15] (enable capture unit)
    2. Write 0 to bits QCAPCTL[5..6] (= CAPCLK = VCLK4/2)
    3. Write 1 to bit QCAPCTL[4] (= CAPCLK = VCLK4/2)
    4. Write 0 to bits QCAPCTL[0..3] (= UPEVNT = QCLK/1)

    Write 1 means setting the flag,  and write 0 clearing the flag. Will the sequence of actions achieve qctmr reset oon every position event? 

    Thanks for the time and support! 

    Best regards,

    Luis

  • 0 in reply to Luis Lanca
    Prodigy 250 points

    Dear Jagadish,

    I am writing to kindly ask you about when you can provide feedback on my previous questions. 

    Best regards, 

    Luís 

  • 0 in reply to Luis Lanca
    TI__Guru 69771 points

    Hi Luis,

    Apologies in the delay response.

    I am on vacation for one week. Today i will try to reproduce your issue and will try to provide an update ASAP.

    --

    Thanks & regards,
    Jagadish.

  • +1 in reply to jagadish gundavarapu
    TI__Guru 69771 points

    Hi Luis,

    Apologies for the delay in the response.

    Luis Lanca said:
    - should the configuration of any used eqep control register (clear/set bits) only be done in one go? 

    No, not necessarily. You can do it in multiple steps as well.

    As you can see the above code is the driver example code in HALCoGen, you can see there are API's to change the control register bits during run time as well.

    Luis Lanca said:
    - control register bits not used should be explicitly sets to the reset values documented in the reference manual?

    No, not necessary to reset the values. You can just even ignore if you are not using the corresponding bits.

    Luis Lanca said:

    - we want to reset of QCTMR on every position event.The Current configuration code for the capture timer sets the memory mapped register QCAPCTL bits in the following sequential order :

    1. Write 1 to bit QCAPCTL[15] (enable capture unit)
    2. Write 0 to bits QCAPCTL[5..6] (= CAPCLK = VCLK4/2)
    3. Write 1 to bit QCAPCTL[4] (= CAPCLK = VCLK4/2)
    4. Write 0 to bits QCAPCTL[0..3] (= UPEVNT = QCLK/1)

    My suggested flow is below:

    1. Disable the capture:

    2. Now set the pre-scalers as per the requirement:

    3. Enable the capture:

    --

    Thanks & regards,
    Jagadish.