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Original question:

TMS570LS1227: When does the eQEP position count overflow occurs?

TMS570LS1227: Clarification on eQEP Index Event Latch

Luis Lanca
Prodigy 250 points
Part Number: TMS570LS1227

Dear all,

In SPNU515c-March 2018 is written "The index event latch interrupt flag (QFLG[IEL]) is set when the position counter is latched to the
QPOSILAT register. The index event latch configuration bits (QEPCTZ[IEL]) are ignored when QEPCTL[PCRM] = 00."

NOTE: I assume QEPCTZ is a typo and should read QEPCTL.

Please confirm my understanding of the quote above: When QEPCTL[PCRM] = 00, even if QEINT[IEL] = 1, QFLG[IEL] is meaningless—and should not be used—because QEPCTL[IEL] configuration bits are ignored.


Thanks a lot for your time!

Best regards,

Luis

  • 0
    TI__Guru 62590 points

    Hi Luis,

    We started working on your issue and will try to provide an update ASAP.

    --

    Thanks & Regards,
    Jagadish.

  • +1 in reply to jagadish gundavarapu
    TI__Guru 62590 points

    Hi Luis,

    First of all apologies for my delayed response. I am on vacation for few days.

    Luis Lanca said:
    NOTE: I assume QEPCTZ is a typo and should read QEPCTL.

    You are right and it is a typo and should be QEPCTL. We will correct this in next revision of TRM.

    Luis Lanca said:
    Please confirm my understanding of the quote above: When QEPCTL[PCRM] = 00, even if QEINT[IEL] = 1, QFLG[IEL] is meaningless—and should not be used—because QEPCTL[IEL] configuration bits are ignored.

    Yes, your understanding is correct. QFLG[IEL] is meaningless and should not be used because QEPCTL[IEL] configuration bits are ignored.

    --

    Thanks & regards,
    Jagadish.