TMS570LS1227: When does the eQEP position count overflow occurs?

static void fn_qep_reg_init_qepctl(qep_reg_t* p_qep_reg) {
    /**
     * Setup eQEP Control Register QEPCTL (SPNU515C, p. 920, p. 921).
     *
     * PCRM: Select Position counter Reset Mode:
     *
     * 0h = Position counter reset on any index event,
     * 1h = Position counter reset on the maximum position,
     * 2h = Position counter reset on the first index event.
     */
    BITMOD_CLR_BITS_16(0x3u, 12u, p_qep_reg->u16_qepctl);

    /* SEI: Enable & Select Strobe event initialization of position counter.
     *
     * 0h = Do nothing (action is disabled).
     */
    BITMOD_CLR_BITS_16(0x3u, 10u, p_qep_reg->u16_qepctl);

    /* IEI: Enable & Select Index event initialization of position counter.
     *
     * 0h = Do nothing (action is disabled),
     * 2h = Initializes the position counter on the rising edge of the QEPI
     *      signal (QPOSCNT = QPOSINIT).
     */
    BITMOD_CLR_BITS_16(0x3u, 8u, p_qep_reg->u16_qepctl);

    /* SWI: Enable / Disable Software Initialization of Position counter.
     *
     * 0h = Do nothing (action is disabled).
     */
    BITMOD_CLR_BIT_16(7u, p_qep_reg->u16_qepctl);

    /* SEL: Select Strobe event latch of position counter.
     *
     * The position counter is latched on the rising edge of QEPS
     * strobe (QPOSSLAT = POSCCNT). Latching on the falling edge is
     * done by inverting the strobe input using the QSP bit in the
     * QDECCTL register.
     *
     * The position counter is latched on the rising edge of QEPS strobe
     * (QPOSSLAT = QPOSCNT).
     */
    BITMOD_CLR_BIT_16(6u, p_qep_reg->u16_qepctl);

    /* IEL: Select Index event latch of position counter.
     * 1h: Latches position counter on rising edge of the index signal.
     */
    BITMOD_CLR_BIT_16(5u, p_qep_reg->u16_qepctl);
    BITMOD_SET_BIT_16(4u, p_qep_reg->u16_qepctl);

    /* QPEN: Quadrature position counter enable/software reset.
     *
     * Reset the eQEP peripheral internal operating flags/read-only
     * registers. Control/configuration registers are not disturbed by a
     * software reset.
     *
     * 0h: Reset the eQEP peripheral internal operating flags/read-only
     *     registers.
     */
    BITMOD_CLR_BIT_16(3u, p_qep_reg->u16_qepctl);

    /* Enable Position Counter (QPEN) (SPNU515C, p. 921).
     * QPEN = 1h: Enable Position Counter
     */
    BITMOD_SET_BIT_16(3u, p_qep_reg->u16_qepctl);

    /* QCLM: Select EQEP capture Latch mode (SPNU515C, p. 921).
     *
     * Latch on position counter read by CPU. Capture timer and
     * capture period values are latched into QCTMRLAT and QCPRDLAT
     * registers when CPU reads the QPOSCNT register.
     *
     * Latch on position counter read by CPU.
     */
    BITMOD_CLR_BIT_16(2u, p_qep_reg->u16_qepctl);

    /* Disable Unit Timer. */
    BITMOD_CLR_BIT_16(1u, p_qep_reg->u16_qepctl);

    /* WDE: eQEP watchdog enable.
     *
     * Disable eQEP watchdog timer.
     */
    BITMOD_CLR_BIT_16(0u, p_qep_reg->u16_qepctl);
}

With BITMOD* documentation:

/**
 * \brief Helpers to set/clear/toggle multiple bits of `uint16_t` value
 *
 * `bits_` must be of unsigned integer type with max. width of `val_`.
 * `pos_` must be unsigned integer or non-negative enumeration type with value
 * < 16 - non-zero-MSB(`bits_`).
 * `val_` must be `uint16_t` type.
 */