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TM4C1294KCPDT: Pin configuration when used as timer pin with actions

Rainer Thaden
Intellectual 330 points
Part Number: TM4C1294KCPDT

Hi all,

I want to use a timer pin to implement a bus protocol, i.e. measure edge times when receiving data and controlling edge times when sending.

0 and 1 are implemented by different high times.

Capturing the edge times when receiving is simple, I expect transmitting 0 and 1s is simply done by using timers with actions,

When transmitting, the pin needs to be open-drain.

When I configure the pin as a timer pin with Tivaware, it is set as a push pull pin

void
GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins)
{
    //
    // Check the arguments.
    //
    ASSERT(_GPIOBaseValid(ui32Port));

    //
    // Make the pin(s) be peripheral controlled.
    //
    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);

    //
    // Set the pad(s) for standard push-pull operation.
    //
    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
}

Is it possible to have this as open drain by doing

GPIOPinTypeTimer(GPIO_PORTL_BASE, GPIO_PIN_6);

GPIOPadConfigSet(GPIO_PORTL_BASE, GPIO_PIN_6, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD)

?

Best regards,

Rainer

  • 0
    TI__Guru**** 191826 points

    Hi Rainer,

    I think it should work. I will suggest you copy the gpio.c file to your project directory, make the change and compile it along with the rest of the project. The change you make will overwrite the prebuilt drlverlib.lib. You can also make the change to the library itself and rebuild the library too.  

  • 0 in reply to Charles Tsai
    Intellectual 330 points

    Hi Charles,

    thanks for the quick response.

    I'm not so much puzzled by how to manage the code but by the pin behaviour.

    I just need this for one pin, so it works for me to add the one line of code after initialization.

    If it's possible to configure the pin as open drain when used with the timer I'm fine with that.

    I'll try and report my findings next week.

    Best regards,

    Rainer

  • +1 in reply to Rainer Thaden
    Intellectual 330 points

    Hi Charles,

    it may work, in principle, however I found out (the hard way) that PL6 and PL7 may not be used in open drain configuration.

    This is stated in a note in the manual

    " Port pins PL6 and PL7 operate as Fast GPIO pads, but have 4-mA drive capability only. GPIO register controls for drive strength, slew rate and open drain have no effect on these pins."

    After using this MCU for years, I simply did not look up if any of the GPIOs may have issues with open drain. Maybe, it's too much to ask for but wouldn't it be possible to catch this with ASSERTS in the DRL code?

    Anyway, during debugging this, I found that the guy reporting strange behaviour in this post

    e2e.ti.com/.../tm4c1294ncpdt-pl6-and-pl7-misbehaving

    was absolutely correct with the strange observation that the pin is doing the opposite of what it's told to if it is configured as open drain.

    That is: configure PL6 as GPIO in open drain mode, set it to high level and, believe it or not, the pin goes low (and vice versa).

    Maybe, this is interesting for anyone stumbling on the same problems.

    Best regards,

    Rainer

  • 0 in reply to Rainer Thaden
    TI__Guru**** 191826 points

    Hi Rainer,

      Thank you to bring up the special case for PL6 and PL7. I missed this myself on the datasheet. Yes, these two pins can only operate with 4mA drive strength. Open drain configuration has no effect on these two pins. I tend to think that open-drain configuration does have some effect on the pins but in a negative way instead of no effect.  I will bookmark this post for future reference in case others stumble on the same observation. 

    Note: Port pins PL6 and PL7 operate as Fast GPIO pads, but have 4-mA drive capability only.
    GPIO register controls for drive strength, slew rate and open drain have no effect on these
    pins. The registers which have no effect are as follows: GPIODR2R, GPIODR4R,
    GPIODR8R, GPIODR12R, GPIOSLR, and GPIOODR.