TMS570LC4357: MibSPI transfer group unable to send 24 bit data.

Pratik Bhagat

Prodigy 50 points

Part Number: TMS570LC4357
Other Parts Discussed in Thread: TMS320F28377D,

Hello Folks,

I am trying to communicate with external device which needs my SPI to send and receive 24 bit data.

I am using Multibuffer mode with number of buffers set to 3.

Following are my configurations:
1) Charlen = 8

2) CSHOLD Bit = SET

3) CSNR are set correctly.

4) All fields of SPIDELAY are set to 0.

5) Four pin configuration with CS, no enable pin

6) WDELAY field of SPI FMT register is set to 0

Observations:

Getting Continuous clock pulse till one Byte data and gap of 70ns approximately followed by another byte.

Attached here is the screenshot of the same.
Here Yellow is the data line on SDI pin and Blue is the SCLK.

My expectation is that I should be getting clock pulse continuously for 24 bit i.e 3 bytes.

Please guide me.

over 1 year ago

0 jagadish gundavarapu over 1 year ago

TI__Guru 70621 points

Hi Pratik,

I handled one similar thread very recently, can you please verify it?

(+) TMS570LS3137: Sending multiple 24 bit transfer groups - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Thanks & regards,
Jagadish.

0 Pratik Bhagat over 1 year ago in reply to jagadish gundavarapu

Prodigy 50 points

Hi Jagadish,

Thank you for replying.

I went through the thread which you have shared.

In my case I am not using DMA. Please help me with some example without DMA transfer of 24 bit.

Also in my case I am not expecting delay in clock pulses between two bytes send as shown in below image with blue arrow.

Please guide me in doing this.

0 jagadish gundavarapu over 1 year ago in reply to Pratik Bhagat

TI__Guru 70621 points

Hi Pratik,

I created example for 24bit transfer without DMA, here it is:

MibSPI_24bitTransfer_LC4357.zip

I tried to eliminate the delay between transfer by configuring different modes but still there is a min delay of 120ns is happening.

May be it is sequencer delay, can you please try at your end as well?

--
Thanks & regards,
Jagadish.

0 Pratik Bhagat over 1 year ago in reply to jagadish gundavarapu

Prodigy 50 points

Hi Jagadish,

Thanks for this example, I tried running the example, for me delay is coming around 70ns.
Attached here are the screenshot of scope.
,

As you can see in the 2nd image, after every byte, getting approx 70ns delay in clock.
Note: Blue is clock line and Yellow is MOSI line.

Apart from this I tried running DMA example as well, the observation remains same for that as well.

Thanks and Regards,

Pratik

0 jagadish gundavarapu over 1 year ago in reply to Pratik Bhagat

TI__Guru 70621 points

Hi Pratik,

Pratik Bhagat said:
As you can see in the 2nd image, after every byte, getting approx 70ns delay in clock.

I don't think we can further reduce this delay,

we can increase it by increasing the WDELAY value, but we can't reduce it anymore as we already configured WDELAY as 0.

We can reduce this delay little by increasing the VCLK frequency to max of 110Mhz

because all these delays are depending on VCLK frequency only and VCLK frequency can be configured to 110Mhz max

Just increase it to 110Mhz and test it once, which is ideally the min CS deactived time we will get.

Thanks & regards,
Jagadish.

0 Gobind Singh1 over 1 year ago in reply to jagadish gundavarapu

Intellectual 640 points

Hi Jagadish,

I tried similar thing with SPI in TMS320F28377D microcontroller and below is the screenshot for both with delay and without delay. (SPI-C, FIFO mode, no interrupts, no DMA) - details are in the thread: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1232356/tms320f28377d-spi-fifo-mode/4687046?tisearch=e2e-sitesearch&keymatch=%252520user%25253A448206#4687046

Are you implying that this is possible in TMS320F28377D and not possible in TMS570LC4357?

Thank you.

Gobind Singh

0 jagadish gundavarapu over 1 year ago in reply to Gobind Singh1

TI__Guru 70621 points

Hi Gobind Singh,

Gobind Singh1 said:
Are you implying that this is possible in TMS320F28377D and not possible in TMS570LC4357?

That is not possible, because here the device directly will not support 24bit transfers and it can only support max data word length 16bit only right.

So, here to transfer 24-bit data we are using three 8-bit transfers with CSHOLD. Even though here we are using CSHOLD we must get some deactivation time in between transfers, and we can't completely eliminate this delay. If the device directly supports 24-bit transfer, then you can't see any delay like this but unfortunately it can only support max of 16bit transfer only.

Thanks & regards,
Jagadish.

0 Gobind Singh1 over 1 year ago in reply to jagadish gundavarapu

Intellectual 640 points

Hi Jagadish,

Thanks for the reply.

Just to clarify, TMS320F28377D also supports only 16 bit data transfers. In my code, I sent 64 bits with word length equal to 8 bits. Total 8 words. So, I think the scenario is the same in both cases.

Also, MibSPI of TMS570LC4357 looks more advanced (more options/settings/registers) than the SPI interface on TMS320F28377D. Was not sure it cannot have zero delay between two words transfer.

Thank you.

Gobind Singh

0 jagadish gundavarapu over 1 year ago in reply to Gobind Singh1

TI__Guru 70621 points

Hi Gobind Singh,

Gobind Singh1 said:
Just to clarify, TMS320F28377D also supports only 16 bit data transfers. In my code, I sent 64 bits with word length equal to 8 bits. Total 8 words. So, I think the scenario is the same in both cases.

Also, MibSPI of TMS570LC4357 looks more advanced (more options/settings/registers) than the SPI interface on TMS320F28377D.

You are right, but in TMS320F28377D device i don't see any delay parameters like T2CDELAY, C2TDELAY and WDELAY

And you can see min of 2VCK cycles of WDELAY will always present and we can't eliminate it completely.

--
Thanks & regards,
Jagadish.

0 Gobind Singh1 over 1 year ago in reply to jagadish gundavarapu

Intellectual 640 points

Hi Jagadish,

There is a delay in TMS320F28377D but the delay can be made 0:

For TMS570LC4357, as you pointed, the minimum delay is 2 VCLK cycles. Understood.

Thanks.

Gobind Singh

0 jagadish gundavarapu over 1 year ago in reply to Gobind Singh1

TI__Guru 70621 points

Hi Gobind Singh,

Gobind Singh1 said:
There is a delay in TMS320F28377D but the delay can be made 0:

Yes, correct.

Thanks & regards,
Jagadish.

0 Pratik Bhagat over 1 year ago in reply to jagadish gundavarapu

Prodigy 50 points

Hi Jagadish,

I understood that we can not completely eliminate the delay between two 8 bit transfer.
As the controller supports 16bit transfers.
My question here is can we use two buffers in MibSPI TGs like (16,8).
So while receiving 24 bit from slave device, first 16 bit will go in first buffer and other will go into second 8 bit buffer.

This thread talks about the same : https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/263971/spi-dma-throughput

I doubt like, if I configure two FMT registers, still how it is going to switch buffers after receiving first 16 bits.

If this is possible could you please help me with this implementation.

Thanks in Advance.

0 jagadish gundavarapu over 1 year ago in reply to Pratik Bhagat

TI__Guru 70621 points

Hi Pratik,

I don't think that method is possible.

For example, we are receiving 24bit from slave device with single CS line, how can we copy first 16bits of data to the first TG and next 8bits to the other TG. We can't chain the TG's like that.

This is method is not possible on my understanding of MibSPI.

If at least there are multiple CS lines

Then we can control one TG with one CS and other TG with other CS but here the scenario is different right.

--
Thanks & regards,
Jagadish.