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TMS570LC4357: "Channel Pending Register" is never cleared after the SCI TX DMA transfer is completed.

Sebastian Sokolowski1
Prodigy 100 points
Part Number: TMS570LC4357

Hello,

From SPNU563A 20.3.1.2 Channel Pending Register (PEND) I see the following information:

"The pending bit is automatically cleared for the following conditions:
• At the end of a frame or a block transfer depending on how the channel is triggered as programmed
in the TTYPE bit field of CHCTRL."

I created a piece of code using halogen and SCI DMA examples (in attachment) which proves that at the end of DMA transmission corresponding PEND bit (5) is still active. Is it expected behavior? That information is needed to trigger another DMA transfer as soon as possible. Do you see any other synchronization method?

DMA2.zip

Regards,

Sebastian

  • +1
    TI__Guru 62590 points

    Hi Sebastian,

    Sebastian Sokolowski1 said:
    I created a piece of code using halogen and SCI DMA examples (in attachment) which proves that at the end of DMA transmission corresponding PEND bit (5) is still active. Is it expected behavior?

    Yes, it is expected behavior for DMA transmission.

    If you go through above highlighted lines, there it is clearly mentioning that DMA request will be generated every time the data is shifted out (CITXSHF register
    and the TD0 are empty). That means even if you configured DMA to transmit some "x" number of bytes after shifting all the bytes again TXSHF register and TD0 will become empty right that means it will again generate the DMA request flag right. 

    I mean after transmitting your required "x" number of bytes, the pending flag will get clear, but you can't notice that because a new request to the DMA will go immediately as TD0 becomes empty.

    See, if you set the DMA for SCI receiving then you can notice the pending clear flag.

    Here i just created one DMA example for receiving:

    Here i am receiving 4 bytes in frame transfer mode, so that means DMA pending flag should clear after every frame i received.

    See here i just received one character to the receiving buffer but still pending flag is in clear only. That means its just set while transferring the frame(0xFF) and it was cleared after shifting the frame to the receive buffer.

    See even after receiving all the frames(Block transfer) completion also no flag channel pending flag will get SET here.

    The difference is DMA RX request will only generate after receiving a new character to the SCI RD register but DMA TX request will generate whenever the SCI TD register empty.

    So, what i did in my previous example is i just sent one more byte after receiving all the bytes(that means DMA completed all block transfer but i send one extra byte after DMA completing it's work), as DMA done block transfer it won't process this extra byte right, so in this case i could see Channel pending flag for SCI DMA receving.

    I hope this clarifies your doubts, and i am attaching my tested example here.

    SCI_DMA_LC4357.zip

    I hope this will clarify your doubts regarding DMA pending flags.

    --

    Thanks & regards,
    Jagadish.