RM57L843: What can cause VIM to call the Phantom Vector interrupt (at 0xFFF82000)?

Hi Marcio,

Not sure why!

Can you go through the below thread, this might be useful:

(+) phantomInterrupt called, unknown reason - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

If issue not rectified even after referring above thread, please share your code if possible so that i can debug the issue.

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Thanks & regards,
Jagadish.

Hello Jagadish, 

The thread you have suggested does not apply to our case.

But I suspect my program is not initialising the VIM correctly, specially because it is running the self-tests (from Safe TI Diagnostic Library) and they make the MPU to reset several times.  

Could you confirm what this routine generated by Halcolgen does? Is it configuring the exception vector base location to HIVECS (0xFFFF0000-0xFFFF001C)? If yes, I believe my program should not call it.

;-------------------------------------------------------------------------------
; Enable Offset via Vic controller
; SourceId : CORE_SourceId_012
; DesignId : CORE_DesignId_005
; Requirements: HL_CONQ_CORE_SR5

    .def     _coreEnableIrqVicOffset_
    .asmfunc

_coreEnableIrqVicOffset_

        mrc   p15, #0, r0,         c1, c0,  #0
        orr   r0,  r0,    #0x01000000
        mcr   p15, #0, r0,         c1, c0,  #0
        bx    lr

    .endasmfunc

Thanks and regards,

Marcio.

Hi Marcio,

Apologies for the delay in the response, here in india we got couple of holidays.

Marcio Borges said:

Could you confirm what this routine generated by Halcolgen does? Is it configuring the exception vector base location to HIVECS (0xFFFF0000-0xFFFF001C)? If yes, I believe my program should not call it.

Yes, it is generated by HALCoGen.

And after verifying my example codes i could see this function is calling in the initializations after systemInit.

And also refer below thread that might helpful for you:

(+) CCS/RM46L852: Which should happen first? _coreEnableIrqVicOffset_ or systemInit - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

--
Thanks & regards,
Jagadish.

Hello,

I believe my program handles interrupts using the "Register vectored interrupts" behaviour, because the CPU executes the instructions placed at 0x18 or 0x1C. This seems to be the default behaviour.

The TRM says that  hardware vectored interrupts behaviour must be explicitly enabled by setting the vector enable (VE) bit in the CP15 R1 register. Thus, I think my program should not call _coreEnableIrqVicOffset_. Am I correct?

Besides that "hardware vectored interrupts" does not handle IFQs and the ESM High interrupt is an IFQ (channel 0).

I have removed _coreEnableIrqVicOffset_ and all IFQs and IRQs seem to continue working.

Regards,
Marcio.