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RM57L843: VIM Interrupt Generation

Rait Raak
Prodigy 20 points
Part Number: RM57L843

Question: Is the interrupt generation in VIM edge or level sensitive? Cannot see anything in the documentation and found two posts from TI employees in this forum claiming opposite.

https://e2e.ti.com/support/microcontrollers/hercules/f/312/p/340076/1188980#1188980

https://e2e.ti.com/support/microcontrollers/hercules/f/312/p/201084/715723#715723

Main reason for asking is one of the comments:

For sending an interrupt to the CPU then you probably shoudl not use this mode because the CPU interrupt controller is level sensitive, and if you clear the request automatically then it may not be there by the time the  CPU gets to service the VIM.  In that case you would get the phantom interrupt vector -- (interrupt that came but disappeared on it's own before the CPU could find out which it was..)

In case of edge sensitive VIM this would not be an issue.

  • 0
    TI__Mastermind 49120 points
    From an application's perspective, there is no difference whether an interrupt request at its source IP is level-triggered or pulse-triggered. The interrupt manager handles either case. The reference manual describes the procedure for addressing interrupt requests.

    The note you reference is specifically for the use of COMPxCLR registers in the RTI module. These allow you to define compare values to automatically clear "RTI compare match" outputs from the RTI module. This functionality is designed so that the compare match condition can be used to trigger system events such as ADC conversions or SPI transfers. When used for these purposes with an automatic clear, care must be taken to not also enable an interrupt for the selected compare match condition.

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Prodigy 20 points

    Can you please point me to the section of the reference manual that describes this situation and forbids interrupt enabling.

  • 0 in reply to Rait Raak
    TI__Mastermind 49120 points
    It is up to the user to decide how to generate the rising and falling edges on the RTI compare event.

    A rising edge is created by the "compare match to set" event in the RTI module.

    A falling edge is created by:
    1) A "compare match to clear" event in the RTI module, OR
    2) By triggering an interrupt to the CPU on a compare match and not using the auto-clear functionality of the RTI module.

    The CPU clearing the interrupt flag creates the "falling edge" on the compare event signal in the second case.

    If you enable both the auto-clear and also interrupt the CPU for the same RTI compare event, the interrupt service routine will not find the flag set any more and will indicate a phantom interrupt.