I'm using HALCoGen 2.09.000 .
In the generated code _c_int00(), i use this function to enable parity check and parity bits memroy mapped,
VIM_EnableRAMParityCheck();
/* Initialize VIM table */
{
unsigned i;
for (i = 0; i < 64U; i++)
{
vimRAM->ISR[i] = s_vim_init[i];
}
}
static void VIM_EnableRAMParityCheck(void)
{
vimParityREG->TEST = 1U; /* parity bits are memory mapped*/
vimParityREG->PARENA = 0xAU; /* VIM parity is enabled*/
}
while debugging, the VIM parity bits updated correctly after VIM RAM initialization.
And i enable VIM parity error in low level interrupt in ESM module.
And also, i use SPI3(master) and SPI1(slave) communicating, and enable SPI1 transfer-complete interrupt in high
level interrupt.
Before spi1HighLevelInterrupt() enters, i change the corresponding parity bit value to a wrong value in VIM RAM
area, and then continue run software, but the software will not enter esmLowLevelInterrupt(), it will goto sys_intvecs.asm and run to here:
prefetchEntry
b prefetchEntry
Why does this happen? and what should do when VIM RAM parity error detectes? and how to test VIM parity error detection? Much thanks.