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LP-AM243: Issue while running Enet CPSW TimeSync PTP Demo

Part Number: LP-AM243

Hi,

I'm using the mcu_plus_sdk_am243x_08_05_00_24 SDK with AM243-LP board. I was trying out the Enet CPSW TimeSync PTP Demo based on the steps mentioned in this page.

But the UART output seems to be different than expected, am attaching the output below:

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Starting NULL Bootloader ...
DMSC Firmware Version 8.5.3--v08.05.03 (Chill Capybar
DMSC Firmware revision 0x8
DMSC ABI revision 3.1
INFO: Bootloader_runCpu:155: CPU r5f1-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU r5f1-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU m4f0-0 is initialized to 400000000 Hz !!!
INFO: Bootloader_loadSelfCpu:207: CPU r5f0-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:207: CPU r5f0-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runSelfCpu:217: All done, reseting self ...
==========================
L2 Multi-channel Test
==========================
Init all peripheral clocks
----------------------------------------------
Enabling clocks!
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

In the expected output the `CpswCpts_ioctl_handler_ENET_TIMESYNC_IOCTL_ADJUST_TIMESTAMP: Setting PPM to 1024` message seem to appear a few times and then the demo should run, Im not sure why its repeated continously afterwards.

Broadcaster is a Linux PC (linuxptp) with NIC as  Ethernet Connection (17) I219-LM

Thanks