MCU-PLUS-SDK-AM243X: EVM AM243x : using more than one external gpio irq

Hi Thomas,

Our expert for this topic is out of office and will return by Nov 27th, please expect a response early that week.

Best Regards,

Sahana

Hi Sahana,

no problem and thanks for the info.

Best regards,

Thomas

Hi Thomas,

Did you select different interrupt router output for both GPIO pins? If possible, could you share the project for me to take a look?

Regards,

Abishek S S

Hello Abishek,

thanks for the quick reply. Yes, I've defined two IRQs. GPIO_PUSH_BUTTON as in the original example (ROUTER7, GPIO1, SPI0_CS1/C13) and a second external pin with the name GPIO_EXTERNAL_IRQ (ROUTER6, GPIO1, PRG0_PRU1_GPO13/T6).

Best regards,

Thomas

By the way, what's the easiest way to upload a small zip file?

Are you not able to attach the zip file here?

I'll try to replicate this in my setup and get back to you.

7317.gpio_input_interrupt_am243x-evm_r5fss0-0_nortos_ti-arm-clang.zip

Thanks a lot.

Hello Abishek,

thanks for the fast support. I will try to use a different gpio pin for the next test and let you know the result.

Best regards,

Thomas

Hello Abishek,

after switching to the following two gpio pins

PRG0_PRU1_GPO14/U6
PRG0_PRU1_GPO15/U5

the error message still looks identical

[Error] Sciclient event config failed!!!
ASSERT: 0.2306s: syscfg/ti_drivers_config.c:Sciclient_gpioIrqSet:143: FALSE failed !!!

I think it's not allowed to configure the struct rmIrqReq twice :

static void Sciclient_gpioIrqSet(void)
{
  int32_t retVal;
  struct tisci_msg_rm_irq_set_req rmIrqReq;
  struct tisci_msg_rm_irq_set_resp rmIrqResp;
  rmIrqReq.valid_params = 0U;
  rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
  rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
  rmIrqReq.global_event = 0U;
  rmIrqReq.src_id = TISCI_DEV_GPIO1;
  rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(34);
  rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0;
  rmIrqReq.dst_host_irq = CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_6;
  rmIrqReq.ia_id = 0U;
  rmIrqReq.vint = 0U;
  rmIrqReq.vint_status_bit_index = 0U;
  rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

 retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);
  if(0 != retVal)
  {
   DebugP_log("[Error] Sciclient event config failed!!!\r\n");
   DebugP_assert(FALSE);
  }
  rmIrqReq.valid_params = 0U;
  rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
  rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
  rmIrqReq.global_event = 0U;
  rmIrqReq.src_id = TISCI_DEV_GPIO1;
  rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(35);
  rmIrqReq.dst_id = TISCI_DEV_R5FSS0_CORE0;
  rmIrqReq.dst_host_irq = CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_7;
  rmIrqReq.ia_id = 0U;
  rmIrqReq.vint = 0U;
  rmIrqReq.vint_status_bit_index = 0U;
  rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

 retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER); // <<<< (*)
  if(0 != retVal)
  {
   DebugP_log("[Error] Sciclient event config failed!!!\r\n");
  DebugP_assert(FALSE);
  }
  return;
}

The second call (*) of Sciclient_rmIrqSet() leads to the error. I think it should be the same on your board.

I think, if you want to use more than one irq gpio pin, you can only configure one pin per bank as "Enable Interrupt Configuration" inside the example.syscfg. The second gpio pin must not have this flag "Enable Interrupt Configuration" set. The following change inside GPIO_bankIsrFxn() works, but I'm not sure if this is really the idea of the IRQ handling on the AM243x?

static void GPIO_bankIsrFxn(void *args)
{
   uint32_t pinNum = (uint32_t) args;
   uint32_t bankNum = GPIO_GET_BANK_INDEX(pinNum);
   uint32_t intrStatus;

   /* Get and clear bank interrupt status */
   intrStatus = GPIO_getBankIntrStatus(gGpioBaseAddr, bankNum);
  GPIO_clearBankIntrStatus(gGpioBaseAddr, bankNum, intrStatus);

  /* Per pin interrupt handling */
   if(intrStatus & GPIO_GET_BANK_BIT_MASK(GPIO_PUSH_BUTTON_PIN))
  {
     gGpioIntrDone1++;
  }

  /* Per pin interrupt handling */
   if(intrStatus & GPIO_GET_BANK_BIT_MASK(GPIO_PUSH_BUTTON_2_PIN))
  {
   gGpioIntrDone2++;
   }
}

Best regards,

Thomas

gpio_input_interrupt_am243x-evm_r5fss0-0_nortos_ti-arm-clang_002.zip

Hi Thomas,

The issue we are having is that sciclient does not allow us to configure the interrupt router for the same bank more than once.

The AM243x gpio interrupt lines are connected to the interrupt router mux MAIN_GPIO_INTRTR_IN. The output, MAIN_GPIO_INTRTR_MAIN_GPIOMUX_INTROUTER0_OUTP, is connected to the dedicated host interrupt lines. To get the gpio irq, the interrupt router mux must be configured to select the output router for the dedicated core.

AM243x devices are TI's k3 architecture devices where resource management and power management are controlled by a dedicated DMSC core (sysfw). To communicate with this firmware, there is a sciclient driver in the SDK.

It's important to note that interrupt router configurations are based on bank, not pin. We encountered a problem where we were attempting to configure the interrupt router for the same bank twice. Sciclient checks resources at runtime and doesn't allow us to configure the interrupt router output for the second time. 

 For now, you can configure the interrupt for one bank and, for other pins in the same bank, don't enable the interrupt configuration in the sysconfig. By doing so, you can run your application without any errors. It was unexpected for sysconfig to allow configuring interrupt router for the same bank again. we will work on improving it as part of the next release.

Please refer this guide for more details on this 

AM243x MCU+ SDK: SCICLIENT (ti.com)

Please let me know if you have any further questions on this.

Thanks & Regards,

Abishek S S

Hi Abishek,

thank you very much for clarifying this problem and for your explanations.

Best regards,

Thomas

Hi Thomas,

I apologize for the confusion. I previously shared some incorrect information regarding the functionality of the Sciclient IRQ set function. After checking with the DMSC firmware team, I can confirm that the Sciclient IRQ set function supports both pin and bank interrupt configuration. However, our current implementation in Sysconfig only allows us to configure bank interrupts.

  rmIrqReq.src_id = TISCI_DEV_GPIO1;
  rmIrqReq.src_index = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX (34);

To route pin interrupts, we need to directly provide the pin number instead of adding TISCI_BANK_SRC_IDX_BASE_GPIO1 (90U).

We will improve GPIO Sysconfig in the next release. For now, please use the workaround.

Similar Thread on AM62x: [FAQ] SK-AM62 : How to configure the GPIO interrupt on AM62X in MCU+SDK. - Processors forum - Processors - TI E2E support forums

If you don't have any further questions, shall I close the thread?

Thank you.

Hi Abishek,

thanks for the correction. I will have a closer look at this next and then implement it as described. I'm also looking forward to the changes in the next release. By the way, I would like to query 8 gpio pin interrupts (possibly sometimes simultaneously) and wonder whether these can be evaluated by the processor core in all cases. Are there conditions which irq requests can be lost? I would be grateful for any information on this topic.

Best regards,

Thomas

Hello Thomas,

When you enable bank interrupts, if all pins are triggered at the same time, you may get only one interrupt in that SOC.

You have only an IRQ and one interrupt number. In that, you have to check which pins interrupts are triggered, and you can process all pin interrupts in the single-Bank IRQ. So, you will not get any lost of irq.

Regards,

S.Anil.

Hello Swargam,

thanks for the quick reply! ... and (I hope) one last question :

"When you enable bank interrupts, if all pins are triggered at the same time, you may get only one interrupt in that SOC."

OK, got it. What would happen (in this case/configuration) if the 8 x GPIO IRQs arrived with small delays of a few us or ns?

Best regards,

Thomas

Hello Thomas,

Thomas Breitung said:

OK, got it. What would happen (in this case/configuration) if the 8 x GPIO IRQs arrived with small delays of a few us or ns?

Yes, this use case is also possible and will come in a real-time application.

Now, let's say that in the 8 GPIO pins, all are triggered at the same time, but due to the long wire connection to the SOC on the PCB, a few are getting delayed.

In this case, for the first time, few are getting triggered and executed, and in the second time, remaining GPIO's would be served and would not lose any.

Regards,

S.Anil.

Hello Swargam,

perfect and many thanks for the quick explanation!

Best regards,

Thomas