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Original question:

AM2632: PBIST / SOC documentation of testable memories

AM2632: PBIST / testable memory regions

Jo Scho
Intellectual 300 points
Part Number: AM2632

Hello,

we use AM2632 in lockstep mode.
That means, our application firmware runs one one core (R50-0) and is monitored by lockstep core (R50-1).

My question concerns the PBIST memeory test functionality, because I do not understand the SDK hints and user guide instructions in detail.

One of our safety goals is, to test the testable memory regions of R50-0.

SDK has some notes to the PBIST:

- PBIST must be run from a different core than being tested. This is because the test is destructive in nature. For this reason also, after BIST test it is necessary to reset the module.

What does this mean in detail? Can we not test the memories of R5-0 from R50-0?
Is a PBIST with a single core controller (or in a dual core in lockstep mode) possible at all?

Here the SDK information:

I tried the SDK example for PBIST on R50-0 and got the following terminal output:

PBIST Application

Starting PBIST failure insertion test on TOP PBIST
PBIST failure Insertion test complete for TOP BIST
PBIST Failure Insertion Test completed in 49 micro secs

Starting PBIST test on TOP PBIST
PBIST complete for R5 STC
PBIST complete for R51 STC
PBIST complete for PBISTROM
PBIST complete for CPSW
PBIST complete for ICSSM
PBIST complete for MBOX
PBIST complete for MCAN
PBIST complete for TPCC
PBIST complete for MSS_L2_1
PBIST complete for MSS_L2_2
PBIST complete for MSS_L2_3
PBIST complete for VIM1 R5SS0
PBIST complete for VIM0 R5SS1
PBIST complete for VIM1 R5SS1
PBIST complete for R5SS1 RAM
PBIST complete for MSS CR5B ATCM0
PBIST complete for MSS CR5B ATCM1
PBIST complete for MSS CR5B BTCM0
PBIST complete for MSS CR5B BTCM1

All tests have passed

Are the listed memory regions memories of R50-0 or R50-1?


Best regards and thanks for your efforts
Jo Scho

  • 0
    TI__Mastermind 26205 points

    Hi Jo,

    As mentioned by you pBIST is destructive in nature and you can't run the pBIST to the memory from where you are executing.

    I have notified our SDL expert to answer on pBIST application in SDK

    Regards,

    Ankur

  • 0 in reply to Ankur Baranwal
    Intellectual 300 points

    Hello Ankur,

    thank you for your answer, but infortunately I still don't understand it.


    What I understand, or what I think, I understand:

    - pBIST is destructive and has to run on another core, than the memory of a core, you want to test.
      Our safety goal is to test all memories of R0-0, because here our firmware should run, R0-1 shall be in lockstep mode.

      e.g. if I want to test memories of R0-0, I have to run pBIST on R0-1, is this correct?


    - we use AM2632 in lockstep mode, like it is configured per default after reset


    There is our problem now. 
    How can we test the memories of R0-0, if we use R0-1 in lockstep mode. Is a pBIST test with lockstep mode even possible?

    To which core do the listed memories belong to? I have run pBIST fpr core 0 example, are these the memories of core R0-1 than?

    (lockstep was active, I think, because we did not change configuration)

    PBIST complete for R5 STC
    PBIST complete for R51 STC
    PBIST complete for PBISTROM
    PBIST complete for CPSW
    PBIST complete for ICSSM
    PBIST complete for MBOX
    PBIST complete for MCAN
    PBIST complete for TPCC
    PBIST complete for MSS_L2_1
    PBIST complete for MSS_L2_2
    PBIST complete for MSS_L2_3
    PBIST complete for VIM1 R5SS0
    PBIST complete for VIM0 R5SS1
    PBIST complete for VIM1 R5SS1
    PBIST complete for R5SS1 RAM
    PBIST complete for MSS CR5B ATCM0
    PBIST complete for MSS CR5B ATCM1
    PBIST complete for MSS CR5B BTCM0
    PBIST complete for MSS CR5B BTCM1

    Best regards
    Jo Scho

  • 0 in reply to Jo Scho
    TI__Mastermind 19375 points

    Hello Jo Scho,

    Not all the memories listed in the log are for R5F cores. Only VIM, ATCM and BTCM are R5F memories. Other memories can be tested from any R5F cores.

    BootROM already does PBIST on below memories.

    PBISTROM (memoryGroupsBitMap =2)
    MSS_L2_0 (memoryGroupsBitMap =10)
    MSS_L2_1 (memoryGroupsBitMap =11)
    MSS CR5A ATCM0 (memoryGroupsBitMap =19)
    MSS CR5A ATCM1 (memoryGroupsBitMap =20)
    MSS CR5A BTCM0 (memoryGroupsBitMap =21)
    MSS CR5A BTCM1 (memoryGroupsBitMap =22)

    For testing CR5B ATCM and BTCM memoires, you can have a small piece of code residing in MSS_L2_0/MSS_L2_1 or CR5A ATCM/BTCM and test.

    For testing R5F VIM, you could save the content of VIM RAM in to other tested memories, initiate the test and poll for test completion. Once test is complete, restore the VIM RAM.

    Thanks and Regards,
    Vishwanath Reddy.