AM2434: R5F Interrupt handling/ interrupt nesting

Alexander Baehr

Part Number: AM2434
Other Parts Discussed in Thread: TMDS243EVM

Hi experts,

I am working with AM243EVM and SDK 09_01_00_41.

We are using FreeRTOS, but have some hard-real-time tasks up to 32 kHz cycle where we intend to use IRQ/FIQ directly by HwiP_construct(). Among those hard-real-time tasks, we also need interrupt nesting.

First, we tried to achieve this goal by using IRQ, because interrupt nesting is available here. However, we found that interrupt handling jitters up to 15µs depending on FreeRTOS load, which is too much for our application. This is much better if we use FIQ, but there is no interrupt nesting here.

- What is the root cause for such a high jitter with IRQ? There seems o be quite a lot of code in FreeRTOS that is executed while interrupts are locked. Is this somehow configurable?

- Could you provide us the code to enable FIQ nesting? ARM documentation says it should be quite the same, but I could not get it to work on the first try.

Alexander

over 2 years ago

0 QJ Wang over 2 years ago

TI__Guru**** 200206 points

Hi Alex,

The processor supports nested IRQ interrupt, which means during the execution of a low priority interrupt service routine (ISR), a high priority service can pre-empt and the low priority ISR is suspended, and resume when the high priority ISR completed. The interrupt latency is normally a lot worse for low priority interrupts. What is the interrupt latency in a best case and in the worst case in your test?

Here is one interrupt latency thread:

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1122978/am2434-am2434-gpio-interrupt-latency

As far as I know, the FIQ doesn't support nested interrupt.

0 Alexander Baehr over 2 years ago in reply to QJ Wang

Intellectual 657 points

Hi QJ,

The interrupt latency ist less than 1µs in best case, which would be fine for us, so we did not measure in the ns range. Worst case is around 15µs. We think it depends on how much code is running under RTOS, or how many RTOS tasks are active.

Your citation also confirms that some 200ns is possible in the NORTOS case. So why isn't it possible with RTOS?

Alexander

0 QJ Wang over 2 years ago in reply to Alexander Baehr

TI__Guru**** 200206 points

Hi Alex,

The interrupt latency in freeRTOS is longer than in non-RTOS, but it should be in the range of 1us time frame if only one interrupt is enabled. If more than one interrupt is enabled, the interrupt with lower priority won't be handled until the priority with higher priority has been processed, so the latency of lower priority interrupt may have much longer latency.

In freeRTOS, one more layer is implemented to enable the interrupt. The IRQ handler is implemented in portASM.s

0 Alexander Baehr over 2 years ago in reply to QJ Wang

Intellectual 657 points

irq_demo_pics.zip

Hi QJ,

please find attached a short demo, based on the enet_lwip_cpsw example, with an added EPWM interrupt.

The interrupt latency is up to 6 µs if the ethernet application is not used (006.png), and up to 8µs if I start iperf on the PC (007.png).

I used TMDS243EVM and TMDS243EC01EVM In the scope shots, magenta is the pwm output (P7.7 on TMDS243EC01EVM), and yellow is interrupt service GPIO (P8.1). Trigger on rising edge of magenta and use infinite persistence.

What am I missing? Can you reproduce there results?

Alexander

0 QJ Wang over 2 years ago in reply to Alexander Baehr

TI__Guru**** 200206 points

Hi Alex,

I don't have an EVM. I will run a test on AM243x LP next Monday.

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AM2434: R5F Interrupt handling/ interrupt nesting