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Original question:

AM2434: DDR initialization of AM2434_ALV

AM2434: DDR initialization of custom RAM with AM2434_ALV

Dominik Fischer
Intellectual 480 points
Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

Hello,

We have chosen AM2434_ALV chip and now have a custom eval-board, which uses a 2Gb LPDDR4 from winbond (www.mouser.de/.../W66BP6NB_W66CP2NQ_WFBGA200_datasheet_A01_001_20200-2909736.pdf)

As far as we understand, there are two options initializing DDR:
1) initializing DDR via CCS Scripts, for this I need to generate a custom GEL file
2) adding a DDR instance in the *.syscfg of a CCS project and specifying the path to the generated *_Reginit.h, building and executing this firmware application

For generating both, the GEL file and *_Reginit.h we used the DDR Subsystem Register Configuration (0.10.01) tool from here (https://dev.ti.com/sysconfig) and set the settings as far as we knew.

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --product "Processor_DDR_Config@0.10.01"
 * @versions {"tool":"1.19.0+3426"}
 */

/**
 * Import the modules used in this configuration.
 */
const DDRSS = scripting.addModule("/DDRSS");

/**
 * Write custom configuration values to the imported modules.
 */
DDRSS.system_cfg_dram_type                = "LPDDR4";
DDRSS.lpddr4.$name                        = "sitara_lpddr4_DDRSS_LPDDR40";
DDRSS.lpddr4.system_cfg_dram_density      = 2;
DDRSS.lpddr4.config_dram_mr2_wl_FS2       = 4;
DDRSS.lpddr4.config_dram_mr11_dq_odt_FS1  = "Disable";
DDRSS.lpddr4.config_dram_mr11_dq_odt_FS2  = "Disable";
DDRSS.lpddr4.config_dram_mr11_ca_odt_FS1  = "Disable";
DDRSS.lpddr4.config_dram_mr11_ca_odt_FS2  = "Disable";
DDRSS.lpddr4.config_dram_mr1_nWR_FS2      = 6;
DDRSS.lpddr4.config_dram_mr22_odte_cs_FS0 = "Disable";
DDRSS.lpddr4.config_dram_mr22_odte_cs_FS1 = "Disable";
DDRSS.lpddr4.config_dram_mr22_odte_cs_FS2 = "Disable";


When executing the GEL script we are stuck at MAIN_Cortex_R5_0_0: GEL Output: Polling PI DONE bit... in AM24_DDR_Initialization_ECC_Disabled(), when using option 2) DDR_Init() is added to generated drivers, however after execution we still cannot load a program to DDR, trying leads to the following error message:

MAIN_Cortex_R5_0_0: GEL Output: CPU reset (soft reset) has been issued through GEL.
MAIN_Cortex_R5_0_0: Trouble Writing Memory Block at 0x80000000 on Page 0 of Length 0x7ff0: (Error -1065 @ 0x80001000) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.12.0.00150) 
MAIN_Cortex_R5_0_0: File Loader: Verification failed: Target failed to write 0x80000000
MAIN_Cortex_R5_0_0: GEL: File: C:\Users\username\workspace_v12\hello_world_ddrINIT_am243x-evm_r5fss0-0_nortos_ti-arm-clang\Debug\hello_world_ddrINIT_am243x-evm_r5fss0-0_nortos_ti-arm-clang.out: Load failed.



Tested with
CCS 12.4.0
MCU+ SDK 09.00.00.35


BTW for including a cutom GEL file I put it into C:\ti\ccs1240\ccs\ccs_base\emulation\gel\AM24x\AM24_DDRSS and modified AM24x_GP_EVM.gel to load our custom GEL-script

    // GEL_LoadGel("$(GEL_file_dir)/AM24x-DDR4-1600MTs.gel");
    GEL_LoadGel("$(GEL_file_dir)/CUSTOM-AM243x-DDRConfig.gel");


Any hints would be highly appreciated.

  • 0
    TI__Guru 55965 points

    Hi Dominik,

    When you switch back to GEL_LoadGel("$(GEL_file_dir)/AM24x-DDR4-1600MTs.gel"); and try the same on AM243x EVM, can you access the 0x80000000 memory area using CCS JTAG?

    If it works, then the issue is with your CUSTOM-AM243x-DDRConfig.gel or your generated *_Reginit.h.

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    Intellectual 480 points

    When you switch back to GEL_LoadGel("$(GEL_file_dir)/AM24x-DDR4-1600MTs.gel"); and try the same on AM243x EVM, can you access the 0x80000000 memory area using CCS JTAG?

    Unfortunately I cannot test, as I don't have a AM243x EVM eval board, I only have a AM64x EVM Board and the custom AM243x Board

    If it works, then the issue is with your CUSTOM-AM243x-DDRConfig.gel or your generated *_Reginit.h.

    Yes, I guess there is a issue with those generated files. However, I don't know what is configured wrong, I hoped that you could give me some hints what could be wrong?

  • 0 in reply to Dominik Fischer
    TI__Guru 55965 points

    Hi Dominik,

    1. The AM243x EVM and the AM64x EVM is the same thing/

    2. You can use the online syscfg tools to generate your CUSTOM-AM243x-DDRConfig.gel or your generated *_Reginit.h:

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    Intellectual 480 points

    Hi Ming,

    thanks for your response. We already used the online syscfg tool to generate our CUSTOM-AM243x-DDRConfig.gel and *_Reginit.h.

    Nevertheless we are still not able to get DDR working, do you have any other hints?

    I also tried to use the config file from AM64x-SK, as this board also uses LPDDR4 RAM, but this didn't solve the issue

        GEL_LoadGel("$(GEL_file_dir)/AM64x-LP4_50_800.gel");

    Kind Regards

    Dominik

  • 0 in reply to Dominik Fischer
    TI__Guru 55965 points

    Hi Dominik,

    How do you use the newly generated CUSTOM-AM243x-DDRConfig.gel and *_Reginit.h?

    For the CUSTOM-AM243x-DDRConfig.gel, you should have used the process described in the following link:

    AM243x MCU+ SDK: EVM Setup (ti.com)

    For *_Reginit.h, you should rebuild the SBL_NULL with the newly generated *_Reginit.h in place, then follow the following link to flash the SBL_NULL into the OSPI flash:

    AM243x MCU+ SDK: EVM Setup (ti.com) 

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    Intellectual 480 points

    Hi Ming,

    CUSTOM-AM243x-DDRConfig.gel

    For the CUSTOM-AM243x-DDRConfig.gel, I used this process (AM243x MCU+ SDK: EVM Setup (ti.com)). I initialized SOC with load_dmsc_hsfs.js and adjusted DDR initialization file (AM24x_GP_EVM.gel) to include my CUSTOM-AM243x-DDRConfig.gel instead of the default one.

    One difference I could see is that after SOC initialization I was not able to connect to DMSC-M3 to see the output: DMSC_Cortex_M3_0: Error connecting to the target: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.12.0.00150)

    *_Reginit.h

    For using the *_Reginit.h I put my custom file in the MCU PLUS SDK to .\source\drivers\ddr\v0\soc\am64x_am243x and built two hello world examples:

    1) the first hello world I am flashing contains the DDR section in sysconfig and specifies the path to the custom *_Reginit.h file. I see that in the generated drivers a DDR_init(&gDdrParams); is added.

    2) after executing this application I try to load another hello world program where I adjusted linker.cmd to put .text data onto DDR

    I chose this path as I currently also have problems flashing the SBL_NULL due to problems with OSPI Flash on our board.

    Kind regards

    Dominik

  • +1 in reply to Dominik Fischer
    Intellectual 480 points

    Update: DDR initialization now seems to work, at least I am able to specify the DDR section in linker files and load a simple hello world example, where my .text section is on DDR.

    What I've changed is I built as suggested the SBL NULL bootloader with our custom *_Reginit.h file. As our OSPI is currently not working, I used the SD Card boot mode and "installed" my custom SBL Null bootloader to the SD card.