Hi Team,
I have custom AM2434_ALV processor connected with 4GB DDR4, pin configuration is same as AM2434 EVM board.
I have following question regarding DDR4
Please guide me.
--
Thanks & Regards,
Divyesh Patel
Hi Ming,
I referred "https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/08_05_00_24/exports/docs/api_guide_am243x/DRIVERS_DDR_PAGE.html" for the DDR configuration.
Tried all 3 methods using
but i am not able to generate .gel file
How to generate .gel file? Please guide what wrong steps i have done.
--
Thanks & Regards,
Divyesh Patel
Hi Ming,
I have created .gel file and replaced in the given link
Use the generated AM243x-DDRConfig.gel to replace the C:\ti\ccs1200\ccs\ccs_base\emulation\gel\AM24x\AM24_DDRSS\AM24x-DDR4-1600MTs.gel
Then run script from Scripts->AM24 DDR Initialization -> AM24 DDR Initialization DDR Enabled/ Disabled both, but still stuck as per the attached image
and 2nd time its got failed as per the attached image
I have even tried with TMDS243GPEVM, with the default SDK configuration, still getting issue
Please guide me.
--
Thanks & Regards,
Divyesh Patel
Hi Ming,
Thank you for your response.
Have you adjusted the DDR4 settings according to your DDR4 chip when you use https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM243x_beta?
Yes, I have done all configuration according to the my DDR4 chip.
I will try with CCS1200.
One more confusion is i have tried with EVM but in that also getting error
I have even tried with TMDS243GPEVM, with the default SDK configuration, still getting issue
why its so?
It should work with EVM bcz SDK is configured according to the EVM, then why it’s getting error
Please help me regarding this , it may give me some hint for my problem.
—
Thanks & Regards,
Divyesh Patel
Hi Divyeh,
I think it may be related to the target configuration file and the load_dmsc.js. I tried CS12.0.0 with MCU+ SDK 08.04.00.17 for AM64x using AM64x GP EVM instead of AM243 GP EVM as the default target configuration. It works properly with the following script:
loadJSFile "C:/ti/mcu_plus_sdk_am64x_08_04_00_17/tools/ccs_load/am64x/load_dmsc.js"
followed by the DDR initialization.
By the way the AM243x GP EVM an AM64x G EVM are the same physically.
Best regards,
Ming
Hi Ming,
I have successfully completed DDR initialization test, Write and Read test with AM2434 EVM.
But in my custom board, initialization & write test is done but unable to complete read test.
Please check my log and help me out.
DMSC_Cortex_M3_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC. DMSC_Cortex_M3_0: GEL Output: Do not run this GEL from any other CPU on the SoC. DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000]. DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000]. DMSC_Cortex_M3_0: GEL Output: This is consistent with the SoC DV assumptions. DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs DMSC_Cortex_M3_0: GEL Output: ATCM Configured. DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set. DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors DMSC_Cortex_M3_0: GEL Output: Bootvectors configured. DMSC_Cortex_M3_0: GEL Output: Programming all PLLs. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL) DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL) DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL) DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL) DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL) DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL) DMSC_Cortex_M3_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 0 (MCU PLL) DMSC_Cortex_M3_0: GEL Output: MCU PLL 0 (MCU PLL) Set. DMSC_Cortex_M3_0: GEL Output: All PLLs programmed. DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress... DMSC_Cortex_M3_0: GEL Output: Powering up MAIN domain peripherals... DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_4B DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_8B DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ADC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUGSS DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPMC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SA2UL DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CPSW3G DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW done. DMSC_Cortex_M3_0: GEL Output: Powering up all MAIN domain peripherals done. DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals. DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_TEST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_M4F DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F done. DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals done. DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done! DMSC_Cortex_M3_0: GEL Output: DMSC_Cortex_M3_0: GEL Output: M4F WFI Vector set into IRAM. MAIN_Cortex_R5_0_0: GEL Output: Running from R5 MAIN_Cortex_R5_0_0: GEL Output: DDR not initialized with R5 connect. Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR. ==== MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR4 Initialization is in progress ... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> ECC Disabled <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 0 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address slice 2 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 2 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> Set PHY registers for all FSPs simultaneously (multicast)... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: Frequency not supported by GEL MAIN_Cortex_R5_0_0: GEL Output: Setting DDR4 frequency... MAIN_Cortex_R5_0_0: GEL Output: Triggering start bit from PI... MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI initialization started... <<<--- MAIN_Cortex_R5_0_0: GEL Output: Triggering start bit from CTL... MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR CTL initialization started... <<<--- MAIN_Cortex_R5_0_0: GEL Output: Polling PI DONE bit... MAIN_Cortex_R5_0_0: GEL Output: pi_int_status = 0x29C02001... MAIN_Cortex_R5_0_0: GEL Output: - PI_INIT_DONE_BIT set: The power-on initialization training in PI has been completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_LVL_DONE_BIT set: The leveling operation has completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_RDLVL_GATE_DONE_BIT set: A read leveling gate training operation has been completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_RDLVL_DONE_BIT set: A read leveling operation has been completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_WRLVL_DONE_BIT set: A write leveling operation has been completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_VREF_DONE_BIT set: A VREF setting operation has been completed. MAIN_Cortex_R5_0_0: GEL Output: - Not documented bit set. MAIN_Cortex_R5_0_0: GEL Output: ctl_int_status = 0x02000004... MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR Initialization completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR4 Initialization is DONE! <<<--- MAIN_Cortex_R5_0_0: GEL Output: Starting Writes Test... MAIN_Cortex_R5_0_0: GEL Output: ...DDR Writes test Done! MAIN_Cortex_R5_0_0: GEL Output: Starting Reads Test: MAIN_Cortex_R5_0_0: Data verification failed at 0x80000000 Expected = 0x03020100 Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: Data verification failed at 0x80000004 Expected = 0x04030201 Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: GEL Output: DDR Reads test Done! MAIN_Cortex_R5_0_0: GEL Output: Starting WrRd Test 1: *wr32_ptr=i MAIN_Cortex_R5_0_0: Data verification failed at 0x80000000 Expected = 0x00000000 Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: Data verification failed at 0x80000004 Expected = 0x01010101 Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: GEL Output: Starting WrRd Test 2: *wr32_ptr=~i MAIN_Cortex_R5_0_0: Data verification failed at 0x80000000 Expected = 0x030100FF Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: Data verification failed at 0x80000004 Expected = 0x0100FFFE Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: GEL Output: !!!!! DDR Basic read/write test Failed !!!!
Which configuration can be wrong for this issue?
Please help me out.
--
Thanks & Regards,
Divyesh Patel
Hi James,
In CCS, can you got to Help->About Code Composer Studio->Installation Details->Sitara Device Support. What is the version number?
I have Sitara Device Support version v1.6.1. While updating it inform no updates, so i think it is the latest version.
I have attached am24x as well as am64x file.
Currently i am using am64x configuration, because earlier when i was trying with am24x then it was unable to initialize DDR and stuck in the "POLLING PI done bit"
Then run script from Scripts->AM24 DDR Initialization -> AM24 DDR Initialization DDR Enabled/ Disabled both, but still stuck as per the attached image
Please help me out.
--
Thanks & Regards,
Divyesh Patel
Hi James,
PFA updated console output.
DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs DMSC_Cortex_M3_0: GEL Output: ATCM Configured. DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set. DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors DMSC_Cortex_M3_0: GEL Output: Bootvectors configured. DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Debugging enabled DMSC_Cortex_M3_0: GEL Output: Programming all PLLs. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x000003FF DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x000003FF DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 10 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000 DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 3 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 9 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #2 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 24 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #2 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #3 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 14 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #3 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #4 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 7 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #4 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #5 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 4 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #5 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #6 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 3 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #6 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #7 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 3 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #7 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #8 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 7 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #8 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #9 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 2 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #9 programmed. DMSC_Cortex_M3_0: GEL Output: Selected Main Domain PLL Controller. DMSC_Cortex_M3_0: GEL Output: Cleared bit 0 in the PLL controller control register. DMSC_Cortex_M3_0: GEL Output: Cleared bit 5 in the PLL Controller control register. DMSC_Cortex_M3_0: GEL Output: PLL controller is now in bypass mode. DMSC_Cortex_M3_0: GEL Output: Set reset isolation to prevent a warm reset from killing the PLL controller. DMSC_Cortex_M3_0: GEL Output: Set PLLDIV1 (output_div1). DMSC_Cortex_M3_0: GEL Output: addr: 0x80410124 = 0x00008000 DMSC_Cortex_M3_0: GEL Output: Clear GOSET. DMSC_Cortex_M3_0: GEL Output: GOSTAT is clear. DMSC_Cortex_M3_0: GEL Output: Set PLLDIV1 (output_div1). DMSC_Cortex_M3_0: GEL Output: Set ALN1. DMSC_Cortex_M3_0: GEL Output: addr: 0x80410104 = 0x00000012 DMSC_Cortex_M3_0: GEL Output: Set OCSEL to 0x12, point C on the observation clock input tree inside the PLL Controller. DMSC_Cortex_M3_0: GEL Output: addr: 0x80410148 = 0x00000002 DMSC_Cortex_M3_0: GEL Output: Set the clock control register to enable the OBSCLK output (bit 1). DMSC_Cortex_M3_0: GEL Output: Set GOSET to 1. DMSC_Cortex_M3_0: GEL Output: GOSTAT is clear. DMSC_Cortex_M3_0: GEL Output: Enable PLL Controller (write to bit 0 in control register). DMSC_Cortex_M3_0: GEL Output: Set GOSET to 0. DMSC_Cortex_M3_0: GEL Output: PLLCTRL reset is cleared. PLLCTRL is free. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x0000007F DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x0000007F DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 7 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000001 DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00001000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 9 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 11 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #2 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 4 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #2 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #3 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 9 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #3 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #4 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 79 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #4 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #5 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 5 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #5 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #6 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 15 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #6 programmed. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x000003FF DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x000003FF DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 10 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000002 DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00002000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 5 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1 DMSC_Cortex_M3_0: GEL Output: i: 1, HSDIV value is -1, don't program this one DMSC_Cortex_M3_0: GEL Output: HSDIV clock output disabled. DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #2 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 8 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #2 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #3 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 5 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #3 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #4 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 17 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #4 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #5 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 7 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #5 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #6 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 7 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #6 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #7 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 17 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #7 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #8 DMSC_Cortex_M3_0: GEL Output: i: 8, HSDIV value is -1, don't program this one DMSC_Cortex_M3_0: GEL Output: HSDIV clock output disabled. DMSC_Cortex_M3_0: GEL Output: HSDIV #8 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #9 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 4 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #9 programmed. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x00000001 DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x00000001 DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 1 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000008 DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00008000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 1 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x00000001 DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x00000001 DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 1 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x0000000C DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x0000C000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 3 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x00000003 DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x00000003 DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 2 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x0000000E DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x0000E000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 2 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 2 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 0 (MCU PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x0000001F DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x0000001F DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 5 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x04040000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000 DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 5 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 24 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #2 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 24 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #2 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #3 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 11 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #3 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #4 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 11 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #4 programmed. DMSC_Cortex_M3_0: GEL Output: Selected MCU Domain PLL Conntroller. DMSC_Cortex_M3_0: GEL Output: Cleared bit 0 in the PLL controller control register. DMSC_Cortex_M3_0: GEL Output: Cleared bit 5 in the PLL Controller control register. DMSC_Cortex_M3_0: GEL Output: PLL controller is now in bypass mode. DMSC_Cortex_M3_0: GEL Output: Set reset isolation to prevent a warm reset from killing the PLL controller. DMSC_Cortex_M3_0: GEL Output: Set PLLDIV1 (output_div1). DMSC_Cortex_M3_0: GEL Output: addr: 0x84020124 = 0x00008000 DMSC_Cortex_M3_0: GEL Output: Clear GOSET. DMSC_Cortex_M3_0: GEL Output: GOSTAT is clear. DMSC_Cortex_M3_0: GEL Output: Set PLLDIV1 (output_div1). DMSC_Cortex_M3_0: GEL Output: Set ALN1. DMSC_Cortex_M3_0: GEL Output: addr: 0x84020104 = 0x00000012 DMSC_Cortex_M3_0: GEL Output: Set OCSEL to 0x12, point C on the observation clock input tree inside the PLL Controller. DMSC_Cortex_M3_0: GEL Output: addr: 0x84020148 = 0x00000002 DMSC_Cortex_M3_0: GEL Output: Set the clock control register to enable the OBSCLK output (bit 1). DMSC_Cortex_M3_0: GEL Output: Set GOSET to 1. DMSC_Cortex_M3_0: GEL Output: GOSTAT is clear. DMSC_Cortex_M3_0: GEL Output: Enable PLL Controller (write to bit 0 in control register). DMSC_Cortex_M3_0: GEL Output: Set GOSET to 0. DMSC_Cortex_M3_0: GEL Output: PLLCTRL reset is cleared. PLLCTRL is free. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: MCU PLL 0 (MCU PLL) Set. DMSC_Cortex_M3_0: GEL Output: All PLLs programmed. DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress... DMSC_Cortex_M3_0: GEL Output: Powering up MAIN domain peripherals... DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_4B DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_8B DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ADC DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUGSS DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPMC DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_1 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SA2UL DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_CLUSTER_0. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: ERROR: module state NOT changed! DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0_PBIST DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_CLUSTER_0 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_0. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: ERROR: module state NOT changed! DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_0 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_1. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_1 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: ERROR: module state NOT changed! DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_1 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_1 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CPSW3G DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW done. DMSC_Cortex_M3_0: GEL Output: Powering up all MAIN domain peripherals done. DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals. DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_TEST DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_M4F DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F done. DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals done. DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done! DMSC_Cortex_M3_0: GEL Output: DMSC_Cortex_M3_0: GEL Output: *****DDR is configured using R5 or A53 GELs DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: M4F WFI Vector set into IRAM. DMSC_Cortex_M3_0: GEL Output: Running from DMSC MAIN_Cortex_R5_0_0: GEL Output: Device Type is GP MAIN_Cortex_R5_0_0: GEL Output: Running from R5 or A53 MAIN_Cortex_R5_0_0: GEL Output: Device Type is GP MAIN_Cortex_R5_0_0: GEL Output: Running from R5 or A53 MAIN_Cortex_R5_0_0: GEL Output: Running from R5 MAIN_Cortex_R5_0_0: GEL Output: DDR not initialized with R5 connect. Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR. ==== MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR4 Initialization is in progress ... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> ECC Enabled <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> After priming ECC memory, enable ECC_CK bit with hotmenu AM64 DDR Memory config --> Enable_TI_InlineECC_CK_During_Reads()<<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 0 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address slice 2 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 2 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> Set PHY registers for all FSPs simultaneously (multicast)... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: Running from R5 or A53 MAIN_Cortex_R5_0_0: GEL Output: Debugging enabled MAIN_Cortex_R5_0_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_400MHz MAIN_Cortex_R5_0_0: GEL Output: hsdiv_value: 3 MAIN_Cortex_R5_0_0: GEL Output: HSDIV reset asserted MAIN_Cortex_R5_0_0: GEL Output: HSDIV divider value programmed. MAIN_Cortex_R5_0_0: GEL Output: HSDIV reset de-asserted MAIN_Cortex_R5_0_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set. MAIN_Cortex_R5_0_0: GEL Output: Setting DDR4 frequency... MAIN_Cortex_R5_0_0: GEL Output: Triggering start bit from PI... MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI initialization started... <<<--- MAIN_Cortex_R5_0_0: GEL Output: Triggering start bit from CTL... MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR CTL initialization started... <<<--- MAIN_Cortex_R5_0_0: GEL Output: Polling PI DONE bit... MAIN_Cortex_R5_0_0: GEL Output: pi_int_status = 0x29C02001... MAIN_Cortex_R5_0_0: GEL Output: - PI_INIT_DONE_BIT set: The power-on initialization training in PI has been completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_LVL_DONE_BIT set: The leveling operation has completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_RDLVL_GATE_DONE_BIT set: A read leveling gate training operation has been completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_RDLVL_DONE_BIT set: A read leveling operation has been completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_WRLVL_DONE_BIT set: A write leveling operation has been completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_VREF_DONE_BIT set: A VREF setting operation has been completed. MAIN_Cortex_R5_0_0: GEL Output: - Not documented bit set. MAIN_Cortex_R5_0_0: GEL Output: ctl_int_status = 0x02000004... MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR Initialization completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR4 Initialization is DONE! <<<--- MAIN_Cortex_R5_0_0: GEL Output: Starting WrRd Test 1: *wr32_ptr=i MAIN_Cortex_R5_0_0: Data verification failed at 0x80000000 Expected = 0x00000000 Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: Data verification failed at 0x80000004 Expected = 0x01010101 Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: GEL Output: Starting WrRd Test 2: *wr32_ptr=~i MAIN_Cortex_R5_0_0: Data verification failed at 0x80000000 Expected = 0x030100FF Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: Data verification failed at 0x80000004 Expected = 0x0100FFFE Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: GEL Output: !!!!! DDR Basic read/write test Failed !!!!
I have found the more option for processor initialization according to your latest version.
PFA image for the reference.
Device is set for the NO BOOT mode only.
--
Thanks & Regards,
Divyesh Patel
Hi James,
I don't think so DDR initialized twice, I tried 3 methods and attached data of scripting console and console output. Please have a look.
Initializing ... (Completed) js:> loadJSFile "C:\ti\mcu_plus_sdk_am243x_08_04_00_17\tools\ccs_load\am243x\load_dmsc.js" Connecting to DMSC_Cortex_M3_0! Fill R5F ATCM memory... Writing While(1) for R5F Loading DMSC Firmware ... C:/ti/mcu_plus_sdk_am243x_08_04_00_17//source/drivers/sciclient/soc/am64x_am243x/sysfw.bin DMSC Firmware Load Done... DMSC Firmware run starting now... Connecting to MCU Cortex_R5_0! Main Boot Mode is 120 Running the board configuration initialization from R5! Happy Debugging!! js:> loadJSFile "C:\ti\mcu_plus_sdk_am243x_08_04_00_17\tools\ccs_load\am243x\load_dmsc.js" Connecting to DMSC_Cortex_M3_0! Fill R5F ATCM memory... Writing While(1) for R5F Loading DMSC Firmware ... C:/ti/mcu_plus_sdk_am243x_08_04_00_17//source/drivers/sciclient/soc/am64x_am243x/sysfw.bin DMSC Firmware Load Done... DMSC Firmware run starting now... Connecting to MCU Cortex_R5_0! Main Boot Mode is 120 Running the board configuration initialization from R5! Happy Debugging!! js:>
and the output of console(including DDR initialization and write_read test) is
DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs DMSC_Cortex_M3_0: GEL Output: ATCM Configured. DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set. DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors DMSC_Cortex_M3_0: GEL Output: Bootvectors configured. DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Debugging enabled DMSC_Cortex_M3_0: GEL Output: Programming all PLLs. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x000003FF DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x000003FF DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 10 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000 DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 3 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 9 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #2 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 24 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #2 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #3 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 14 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #3 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #4 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 7 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #4 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #5 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 4 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #5 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #6 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 3 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #6 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #7 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 3 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #7 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #8 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 7 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #8 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #9 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 2 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #9 programmed. DMSC_Cortex_M3_0: GEL Output: Selected Main Domain PLL Controller. DMSC_Cortex_M3_0: GEL Output: Cleared bit 0 in the PLL controller control register. DMSC_Cortex_M3_0: GEL Output: Cleared bit 5 in the PLL Controller control register. DMSC_Cortex_M3_0: GEL Output: PLL controller is now in bypass mode. DMSC_Cortex_M3_0: GEL Output: Set reset isolation to prevent a warm reset from killing the PLL controller. DMSC_Cortex_M3_0: GEL Output: Set PLLDIV1 (output_div1). DMSC_Cortex_M3_0: GEL Output: addr: 0x80410124 = 0x00008000 DMSC_Cortex_M3_0: GEL Output: Clear GOSET. DMSC_Cortex_M3_0: GEL Output: GOSTAT is clear. DMSC_Cortex_M3_0: GEL Output: Set PLLDIV1 (output_div1). DMSC_Cortex_M3_0: GEL Output: Set ALN1. DMSC_Cortex_M3_0: GEL Output: addr: 0x80410104 = 0x00000012 DMSC_Cortex_M3_0: GEL Output: Set OCSEL to 0x12, point C on the observation clock input tree inside the PLL Controller. DMSC_Cortex_M3_0: GEL Output: addr: 0x80410148 = 0x00000002 DMSC_Cortex_M3_0: GEL Output: Set the clock control register to enable the OBSCLK output (bit 1). DMSC_Cortex_M3_0: GEL Output: Set GOSET to 1. DMSC_Cortex_M3_0: GEL Output: GOSTAT is clear. DMSC_Cortex_M3_0: GEL Output: Enable PLL Controller (write to bit 0 in control register). DMSC_Cortex_M3_0: GEL Output: Set GOSET to 0. DMSC_Cortex_M3_0: GEL Output: PLLCTRL reset is cleared. PLLCTRL is free. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x0000007F DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x0000007F DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 7 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000001 DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00001000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 9 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 11 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #2 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 4 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #2 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #3 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 9 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #3 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #4 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 79 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #4 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #5 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 5 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #5 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #6 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 15 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #6 programmed. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x000003FF DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x000003FF DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 10 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000002 DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00002000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 5 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1 DMSC_Cortex_M3_0: GEL Output: i: 1, HSDIV value is -1, don't program this one DMSC_Cortex_M3_0: GEL Output: HSDIV clock output disabled. DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #2 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 8 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #2 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #3 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 5 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #3 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #4 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 17 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #4 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #5 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 7 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #5 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #6 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 7 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #6 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #7 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 17 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #7 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #8 DMSC_Cortex_M3_0: GEL Output: i: 8, HSDIV value is -1, don't program this one DMSC_Cortex_M3_0: GEL Output: HSDIV clock output disabled. DMSC_Cortex_M3_0: GEL Output: HSDIV #8 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #9 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 4 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #9 programmed. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x00000001 DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x00000001 DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 1 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000008 DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00008000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 1 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x00000001 DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x00000001 DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 1 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x0000000C DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x0000C000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 3 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x00000003 DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x00000003 DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 2 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x0000000E DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x0000E000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 2 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 2 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set. DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 0 (MCU PLL) DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs. DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs. DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x0000001F DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x0000001F DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 5 DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information. DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming. DMSC_Cortex_M3_0: GEL Output: For debugging: DMSC_Cortex_M3_0: GEL Output: Base address: 0x04040000 DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000 DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000 DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020 DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1 DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR. DMSC_Cortex_M3_0: GEL Output: Disabled PLL DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC. DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator. DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register. DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider. DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register. DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register. DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register. DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 5 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 24 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #2 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 24 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #2 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #3 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 11 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #3 programmed. DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #4 DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 11 DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed. DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted. DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted DMSC_Cortex_M3_0: GEL Output: HSDIV #4 programmed. DMSC_Cortex_M3_0: GEL Output: Selected MCU Domain PLL Conntroller. DMSC_Cortex_M3_0: GEL Output: Cleared bit 0 in the PLL controller control register. DMSC_Cortex_M3_0: GEL Output: Cleared bit 5 in the PLL Controller control register. DMSC_Cortex_M3_0: GEL Output: PLL controller is now in bypass mode. DMSC_Cortex_M3_0: GEL Output: Set reset isolation to prevent a warm reset from killing the PLL controller. DMSC_Cortex_M3_0: GEL Output: Set PLLDIV1 (output_div1). DMSC_Cortex_M3_0: GEL Output: addr: 0x84020124 = 0x00008000 DMSC_Cortex_M3_0: GEL Output: Clear GOSET. DMSC_Cortex_M3_0: GEL Output: GOSTAT is clear. DMSC_Cortex_M3_0: GEL Output: Set PLLDIV1 (output_div1). DMSC_Cortex_M3_0: GEL Output: Set ALN1. DMSC_Cortex_M3_0: GEL Output: addr: 0x84020104 = 0x00000012 DMSC_Cortex_M3_0: GEL Output: Set OCSEL to 0x12, point C on the observation clock input tree inside the PLL Controller. DMSC_Cortex_M3_0: GEL Output: addr: 0x84020148 = 0x00000002 DMSC_Cortex_M3_0: GEL Output: Set the clock control register to enable the OBSCLK output (bit 1). DMSC_Cortex_M3_0: GEL Output: Set GOSET to 1. DMSC_Cortex_M3_0: GEL Output: GOSTAT is clear. DMSC_Cortex_M3_0: GEL Output: Enable PLL Controller (write to bit 0 in control register). DMSC_Cortex_M3_0: GEL Output: Set GOSET to 0. DMSC_Cortex_M3_0: GEL Output: PLLCTRL reset is cleared. PLLCTRL is free. DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register. DMSC_Cortex_M3_0: GEL Output: PLL is locked. DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. DMSC_Cortex_M3_0: GEL Output: MCU PLL 0 (MCU PLL) Set. DMSC_Cortex_M3_0: GEL Output: All PLLs programmed. DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress... DMSC_Cortex_M3_0: GEL Output: Powering up MAIN domain peripherals... DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_4B DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_8B DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ADC DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUGSS DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPMC DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_1 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SA2UL DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_CLUSTER_0. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: ERROR: module state NOT changed! DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0_PBIST DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_CLUSTER_0 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_0. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: ERROR: module state NOT changed! DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_0 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_1. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_1 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: ERROR: module state NOT changed! DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_1 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_1 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1 DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1 done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CPSW3G DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW done. DMSC_Cortex_M3_0: GEL Output: Powering up all MAIN domain peripherals done. DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals. DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_TEST DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU done. DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_M4F DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F done. DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals done. DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done! DMSC_Cortex_M3_0: GEL Output: DMSC_Cortex_M3_0: GEL Output: *****DDR is configured using R5 or A53 GELs DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: Running from DMSC DMSC_Cortex_M3_0: GEL Output: M4F WFI Vector set into IRAM. DMSC_Cortex_M3_0: GEL Output: Running from DMSC MAIN_Cortex_R5_0_0: GEL Output: Device Type is GP MAIN_Cortex_R5_0_0: GEL Output: Running from R5 or A53 MAIN_Cortex_R5_0_0: GEL Output: Device Type is GP MAIN_Cortex_R5_0_0: GEL Output: Running from R5 or A53 MAIN_Cortex_R5_0_0: GEL Output: Running from R5 MAIN_Cortex_R5_0_0: GEL Output: DDR not initialized with R5 connect. Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR. ==== MAIN_Cortex_R5_0_0: GEL Output: PI Initialization has not been triggered. MAIN_Cortex_R5_0_0: GEL Output: CTL Initialization has not been triggered. MAIN_Cortex_R5_0_0: GEL Output: CTL Initialization has not completed. MAIN_Cortex_R5_0_0: GEL Output: PI Initialization has not completed. MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR4 Initialization is in progress ... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> ECC Disabled <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 0 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address slice 2 programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 2 programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming in progress.. <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> Set PHY registers for all FSPs simultaneously (multicast)... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: Running from R5 or A53 MAIN_Cortex_R5_0_0: GEL Output: Debugging enabled MAIN_Cortex_R5_0_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_400MHz MAIN_Cortex_R5_0_0: GEL Output: hsdiv_value: 3 MAIN_Cortex_R5_0_0: GEL Output: HSDIV reset asserted MAIN_Cortex_R5_0_0: GEL Output: HSDIV divider value programmed. MAIN_Cortex_R5_0_0: GEL Output: HSDIV reset de-asserted MAIN_Cortex_R5_0_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set. MAIN_Cortex_R5_0_0: GEL Output: Setting DDR4 frequency... MAIN_Cortex_R5_0_0: GEL Output: Triggering start bit from PI... MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI initialization started... <<<--- MAIN_Cortex_R5_0_0: GEL Output: Triggering start bit from CTL... MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR CTL initialization started... <<<--- MAIN_Cortex_R5_0_0: GEL Output: Polling PI DONE bit... MAIN_Cortex_R5_0_0: GEL Output: pi_int_status = 0x29C02001... MAIN_Cortex_R5_0_0: GEL Output: - PI_INIT_DONE_BIT set: The power-on initialization training in PI has been completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_LVL_DONE_BIT set: The leveling operation has completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_RDLVL_GATE_DONE_BIT set: A read leveling gate training operation has been completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_RDLVL_DONE_BIT set: A read leveling operation has been completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_WRLVL_DONE_BIT set: A write leveling operation has been completed. MAIN_Cortex_R5_0_0: GEL Output: - PI_VREF_DONE_BIT set: A VREF setting operation has been completed. MAIN_Cortex_R5_0_0: GEL Output: - Not documented bit set. MAIN_Cortex_R5_0_0: GEL Output: ctl_int_status = 0x02000004... MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR Initialization completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR4 Initialization is DONE! <<<--- MAIN_Cortex_R5_0_0: GEL Output: PI Initialization has been triggered. MAIN_Cortex_R5_0_0: GEL Output: CTL Initialization has been triggered. MAIN_Cortex_R5_0_0: GEL Output: CTL Initialization has been completed. MAIN_Cortex_R5_0_0: GEL Output: PI Initialization has been completed. MAIN_Cortex_R5_0_0: GEL Output: Starting WrRd Test 1: *wr32_ptr=i MAIN_Cortex_R5_0_0: Data verification failed at 0x80000000 Expected = 0x00000000 Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: Data verification failed at 0x80000004 Expected = 0x01010101 Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: GEL Output: Starting WrRd Test 2: *wr32_ptr=~i MAIN_Cortex_R5_0_0: Data verification failed at 0x80000000 Expected = 0x030100FF Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: Data verification failed at 0x80000004 Expected = 0x0100FFFE Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: GEL Output: !!!!! DDR Basic read/write test Failed !!!!
According to this during running "loadJSFile "C:\ti\mcu_plus_sdk_am243x_08_04_00_17\tools\ccs_load\am243x\load_dmsc.js" DDR initialization got failed as per the below image.
So later, i initialized through "scripts->AM64 DDR initialization->AM64_DDR_Initialization_ECC_Disabled", then again i check the DDR status. So its initialized successfully.
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR Initialization completed... <<<--- MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR4 Initialization is DONE! <<<--- MAIN_Cortex_R5_0_0: GEL Output: PI Initialization has been triggered. MAIN_Cortex_R5_0_0: GEL Output: CTL Initialization has been triggered. MAIN_Cortex_R5_0_0: GEL Output: CTL Initialization has been completed. MAIN_Cortex_R5_0_0: GEL Output: PI Initialization has been completed. MAIN_Cortex_R5_0_0: GEL Output: Starting WrRd Test 1: *wr32_ptr=i
But after that if i will do write_read test through Script, then its failed.
MAIN_Cortex_R5_0_0: Data verification failed at 0x80000000 Expected = 0x00000000 Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: Data verification failed at 0x80000004 Expected = 0x01010101 Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: GEL Output: Starting WrRd Test 2: *wr32_ptr=~i MAIN_Cortex_R5_0_0: Data verification failed at 0x80000000 Expected = 0x030100FF Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: Data verification failed at 0x80000004 Expected = 0x0100FFFE Actual= 0xFFFFFFFF MAIN_Cortex_R5_0_0: GEL Output: !!!!! DDR Basic read/write test Failed !!!!
I have tried with EVM, in that if i follow the method-1 sequence then I am able to run all test successfully. Please note it.
If i am missing any sequence, then please provide me the initialization sequence. I will try with that.
Please help me out.
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Thanks & Regards,
Divyesh Patel
Hi James,
PFA image, DDR write/read test is passed.
Thank you so much for your support and guidance :-)
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Thanks & Regards,
Divyesh Patel
