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AM2434: DDR initialization of AM2434_ALV

Divyesh Patel
Intellectual 765 points
Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

Hi Team,

I have custom AM2434_ALV processor connected with 4GB DDR4, pin configuration is same as AM2434 EVM board.

I have following question regarding DDR4

  1. I want to configure DDR with processor. Which settings i have to implement to get it done?
  2. I have tried with the default AM2434_EVM DDR script and its stuck in the attached image.

Please guide me.

--

Thanks & Regards,

Divyesh Patel

  • 0
    TI__Mastermind 48755 points

    Hi Divyesh,

    The DDR initialization in the gel file is for the DDR (8MB) used on the AM243x EVM. You may need to adjust it according to the size, timing etc. for the DDR used on your custom board. The file does the DDR initialization for AM243x EVM is at

    C:\ti\ccs1200\ccs\ccs_base\emulation\gel\AM24x\AM24_DDRSS\AM24x_GP_EVM.gel

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    Intellectual 765 points

    Hi Ming,

    Thank you for your message.

    Could you please provide me some procedures or references?

    It will be very helpful for me.

    —

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Mastermind 48755 points

    Hi Divyesh,

    The DDR4 configuration tools and documentation are not in ideal situation. Here is what we have so far:

    1. Go to SysConfig (ti.com) and add a new DDR4 instance

    2. Use the generated AM243x-DDRConfig.gel to replace the C:\ti\ccs1200\ccs\ccs_base\emulation\gel\AM24x\AM24_DDRSS\AM24x-DDR4-1600MTs.gel

    3. re-run the load_dmdsc.js and the AM2434_EVM DDR script.

    You can also adjust the following:

    1. DDR Memory Type

    2. System Configuration

    3. DRAM Timing A/B

    4. IO Control A/B

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    Intellectual 765 points

    Hi Ming,

    Thank you for your guidance.

    I am using ccs1110, does it work with it?

    or need to go with ccs1200?

    —

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    Intellectual 765 points

    Hi Ming,

    I referred "https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/08_05_00_24/exports/docs/api_guide_am243x/DRIVERS_DDR_PAGE.html" for the DDR configuration.

    Tried all 3 methods using

    1. https://dev.ti.com/sysconfig
    2. with CCS example &
    3. Sysconfig tool

    but i am not able to generate .gel file

    How to generate .gel file? Please guide what wrong steps i have done.

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Mastermind 48755 points

    Hi Divyesh,

    It should work for CCS 11.1 too. Please try the steps I suggested in previous post:

    ---------------------------

    The DDR4 configuration tools and documentation are not in ideal situation. Here is what we have so far:

    1. Go to https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM243x_beta and add a new DDR4 instance: 

    2. Use the generated AM243x-DDRConfig.gel to replace the C:\ti\ccs1200\ccs\ccs_base\emulation\gel\AM24x\AM24_DDRSS\AM24x-DDR4-1600MTs.gel

    3. re-run the load_dmdsc.js and the AM2434_EVM DDR script.

    You can also adjust the following:

    1. DDR Memory Type

    2. System Configuration

    3. DRAM Timing A/B

    4. IO Control A/B

    -----------------------------

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    Intellectual 765 points

    Hi Ming,

    I have created .gel file and replaced in the given link

    Ming Wei said:
    Use the generated AM243x-DDRConfig.gel to replace the C:\ti\ccs1200\ccs\ccs_base\emulation\gel\AM24x\AM24_DDRSS\AM24x-DDR4-1600MTs.gel

    Then run script from Scripts->AM24 DDR Initialization -> AM24 DDR Initialization DDR Enabled/ Disabled both, but still stuck as per the attached image

    and 2nd time its got failed as per the attached image

    I have even tried with TMDS243GPEVM, with the default SDK configuration, still getting issue

    Please guide me.

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Mastermind 48755 points

    Hi Divyesh,

    The DDR4 configuration is very complicated, and it is highly dependent to the DDR4 you used.

    Have you adjusted the DDR4 settings according to your DDR4 chip when you use https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM243x_beta?

    For AM243x GP EVM, you may try it with the latest MCU+ SDK 08.05.00.24 and CCS12.

    Best regars,

    Ming 

  • 0 in reply to Ming Wei
    Intellectual 765 points

    Hi Ming,

    Thank you for your response.

    Ming Wei said:
    Have you adjusted the DDR4 settings according to your DDR4 chip when you use https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM243x_beta?

    Yes, I have done all configuration according to the my DDR4 chip.

    I will try with CCS1200.

    One more confusion is i have tried with EVM but in that also getting error

    Divyesh Patel said:

    I have even tried with TMDS243GPEVM, with the default SDK configuration, still getting issue

    why its so?

    It should work with EVM bcz SDK is configured according to the EVM, then why it’s getting error

    Please help me regarding this , it may give me some hint for my problem.

    —

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Mastermind 48755 points

    Hi Divyeh,

    I think it may be related to the target configuration file and the load_dmsc.js. I tried CS12.0.0 with MCU+ SDK 08.04.00.17 for AM64x using AM64x GP EVM instead of AM243 GP EVM as the default target configuration. It works properly with the following script:

    loadJSFile "C:/ti/mcu_plus_sdk_am64x_08_04_00_17/tools/ccs_load/am64x/load_dmsc.js"

    followed by the DDR initialization.

    By the way the AM243x GP EVM an AM64x G EVM are the same physically.

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    Intellectual 765 points

    Hi Ming,

    I have successfully completed DDR initialization test, Write and Read test with AM2434 EVM.

    But in my custom board, initialization & write test is done but unable to complete read test.

    Please check my log and help me out.

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    DMSC_Cortex_M3_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
    DMSC_Cortex_M3_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
    DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
    DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000].
    DMSC_Cortex_M3_0: GEL Output: This is consistent with the SoC DV assumptions.
    DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
    DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
    DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
    DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors
    DMSC_Cortex_M3_0: GEL Output: Bootvectors configured.
    DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set.
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Which configuration can be wrong for this issue?

    Please help me out.

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Mastermind 48755 points

    Hi Divyesh,

    Can you share the spec of your DDR4 chip, the sysconfig settings and the gel file generated for your DDR4 chip?

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    Intellectual 765 points

    Hi Ming,

    I have 4GB DDR4 micron chip and its part number is MT40A256M16LY-062E:F TR, its datasheet is attached here.

    micron_technology_mict_s_a0005091295_1-1764159.pdf

    and also its sysconfig and gel

    800.zip

    Please review and give me some suggestions.

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Mastermind 48755 points

    Hi Divyesh,

    Thanks a lot for sending the part number and the data sheet. I will forward this to our DDR4 expert for further help. It may take some time.

    Thank you very much for choosing TI device and appreciate your patience.

  • 0 in reply to Ming Wei
    Intellectual 765 points

    Hi Ming,

    Thank you for your support.

    I will wait for your feedback.

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Guru* 79810 points

    Some of your latency parameters were incorrectly input into the tool.  These need to be taken from the speed bin tables in the DDR datasheet for your operating speed. Try with: CL=14 and CWL = 9

    REgards,

    James

  • 0 in reply to JJD
    Intellectual 765 points

    Hi James,

    Thank you for your suggestion.

    JJD said:
    Try with: CL=14 and CWL = 9

    I tried, but still same error. Is there any other parameters placed incorrectly?

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Guru* 79810 points

    Something is wrong with your GEL.  Line 137 shows "Frequency not supported by GEL"

    In CCS, can you got to Help->About Code Composer Studio->Installation Details->Sitara Device Support.  What is the version number?  I think the latest is 1.6.3, see if you can update that package and retry.  

    If that doesn't help, please zip up the directory C:\ti\ccs1200\ccs\ccs_base\emulation\gel\am24x and post here, i will take a look.  

    Regards,

    James

  • 0 in reply to JJD
    Intellectual 765 points

    Hi James,

    JJD said:
    In CCS, can you got to Help->About Code Composer Studio->Installation Details->Sitara Device Support.  What is the version number?

    I have Sitara Device Support version v1.6.1. While updating it inform no updates, so i think it is the latest version.

    I have attached am24x as well as am64x file.

    AM64x.zipAM24x.zip

    Currently i am using am64x configuration, because earlier when i was trying with am24x then it was unable to initialize DDR and stuck in the "POLLING PI done  bit"

    Divyesh Patel said:

    Then run script from Scripts->AM24 DDR Initialization -> AM24 DDR Initialization DDR Enabled/ Disabled both, but still stuck as per the attached image

    Please help me out.

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Guru* 79810 points

    Hi Divyesh, it appears the update isn't working either!  Let just completely replace all the GELs:

    -rename C:\ti\ccs1200\ccs\ccs_base\emulation\gel\am64x to am64x_old

    - unzip the attachment  to the same directory so you get a fresh set of GELs for am64x

    -you might need to regenerate your target configuration for your board

    -perform the DDR init and write/read tests like you did previously (ensure that no javascripts run in the scripting console)

    -send the console output if it is still not working 

    /cfs-file/__key/communityserver-discussions-components-files/908/0358.AM64x.zip

    Regards,

    James

  • 0 in reply to JJD
    Intellectual 765 points

    Hi JJD,

    I tried with above configuration, but still getting same error.

    PFA console output.

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    DMSC_Cortex_M3_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
    DMSC_Cortex_M3_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
    DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
    DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000].
    DMSC_Cortex_M3_0: GEL Output: This is consistent with the SoC DV assumptions.
    DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
    DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
    DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
    DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors
    DMSC_Cortex_M3_0: GEL Output: Bootvectors configured.
    DMSC_Cortex_M3_0: GEL Output: Debugging enabled
    DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
    DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs.
    DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs.
    DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x000003FF
    DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x000003FF
    DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 10
    DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
    DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet
    DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    and do i need to change board_ddrReginit.h file from the following path

    C:\ti\mcu_plus_sdk_am243x_08_04_00_17\source\drivers\ddr\v0\soc\am64x_am243x

    Because its mentioned,  in the Readme file of sysconfig.

    README.txt
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    # AM64x\AM62x\AM243x\AM62Ax DDR Register Configuration (v9.05)
    ## Procedure:
    1) Select Add button at the top and choose the DDR Memory Type. Fields will be populated with default values for AM64x\AM62x\AM243x\AM62Ax EVMs<br>
    2) Modify parameters based on your DDR device. Hover mouse pointer over each parameter and choose the help icon (?) for more explanation<br>
    3) The 'Generated Files' section on the right has output files for your software (uboot, RTOS, or GEL) that can be saved. A SysConfig configuration script can also be saved and then reloaded at a later time using File->Open in Sysconfg.
    ### GEL
    The resulting .gel file should be placed in the CCS installation for your device, for example ccs\ccs_base\emulation\gel\AM64x\AM64_DDRSS, and loaded using a GEL_LoadGEL instruction (see example in ccs\ccs_base\emulation\gel\AM64x\AM64_DDRSS\AM64x_GP_EVM.gel)
    ### CMM
    The resulting .cmm file should be placed in the Lautherbach installation for your device.
    ### Linux u-boot
    The resulting .dtsi file should be placed in arch/arm/dts, and the include statement in k3-am642-r5-<board>.dts (eg., k3-am642-r5-evm.dts for the GP EVM, or k3-am642-r5-sk.dts for the StarterKit) should reference the new .dtsi file. The DDR driver will properly set the DDR frequency and initialize the DDR controller using the information in this .dtsi file
    ### MCU+ SDK (RTOS)
    The resulting .h file should be placed in mcu_plus_sdk_<device>_<version>\source\drivers\ddr\v0\soc\am64x_am243x
    and included by using the SysConfig for SDK tool when building your code. Please refer to the SDK API Guide mcu_plus_sdk_<device>_<version>\docs\api_guide_am64x\DRIVERS_DDR_PAGE.html for more information
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Please help me out.

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Guru* 79810 points

    Eventually, the board_ddrReginit.h will need to be changed, but this should not be used when you are initializing the board with the GELs.  That's why i asked if and javascripts are being used.  Ensure that you are not running any javascript files in the scripting console.  Also ensure that no other boot media are booted from when powering the board.  To ensure this, set your boot mode to No Boot Mode, or ensure that your boot media is erased or removed (as in SD card).  Are you running any javascript or unintentionally booting from your boot media?

    After a failure with the latest configuration, can you send a register dump by using the following GEL script:  Scripts->AM64 DDRSS Debug->Memory Debug->AM64 DDRSS CTL PI PHY MemDump

    Regards,

    James

  • 0 in reply to JJD
    Intellectual 765 points

    Hi James,

    PFA load_dmsc.js which i am running for initialization.

    load_dmsc.zip

    JJD said:
    To ensure this, set your boot mode to No Boot Mode, or ensure that your boot media is erased or removed (as in SD card). 

    It is set in the NO BOOT mode.

    Waiting for your feedback.

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    Intellectual 765 points

    Hi James,

    PFA updated console output.

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    DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
    DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
    DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
    DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors
    DMSC_Cortex_M3_0: GEL Output: Bootvectors configured.
    DMSC_Cortex_M3_0: GEL Output: Running from DMSC
    DMSC_Cortex_M3_0: GEL Output: Debugging enabled
    DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
    DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs.
    DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs.
    DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x000003FF
    DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x000003FF
    DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 10
    DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
    DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet
    DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
    DMSC_Cortex_M3_0: GEL Output: For debugging:
    DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
    DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000
    DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

     

    I have found the more option for processor initialization according to your latest version.

    PFA image for the reference.

    Device is set for the NO BOOT mode only.

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Guru* 79810 points

    Hi Divyesh, i'm pretty sure your problem is that you are initializing the DDR twice (once using the javascript, and once using the GEL), this will result in failures.  You should only do one or the other. 

    If you just run the javascript, it should be initializing the DDR, so be sure to put in the latest  board_ddrReginit.h.  Once this is run, you should not have to run any GELs.  Just go directly to the read/write GEL script to test the memory.

    Alternatively, you can run the GELs to setup the PLL/PSCs and initialize the DDR, just to see if you can access memory properly.  You should not run the javascript after this.  After the GELs are run, you can check the memory with the read/write GEL script

    Regards,

    James

      

  • 0 in reply to JJD
    Intellectual 765 points

    Hi James,

    I don't think so DDR initialized twice, I tried 3 methods and attached data of scripting console and console output. Please have a look.

    1. Method-1(Loading JavaScript and DDR initialization)
      • According to guide at every power reset, i need to run this script in NO BOOT mode. So i have loaded java script from "loadJSFile "C:\ti\mcu_plus_sdk_am243x_08_04_00_17\tools\ccs_load\am243x\load_dmsc.js""

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        Initializing ... (Completed)
        js:> loadJSFile "C:\ti\mcu_plus_sdk_am243x_08_04_00_17\tools\ccs_load\am243x\load_dmsc.js"
        Connecting to DMSC_Cortex_M3_0!
        Fill R5F ATCM memory...
        Writing While(1) for R5F
        Loading DMSC Firmware ... C:/ti/mcu_plus_sdk_am243x_08_04_00_17//source/drivers/sciclient/soc/am64x_am243x/sysfw.bin
        DMSC Firmware Load Done...
        DMSC Firmware run starting now...
        Connecting to MCU Cortex_R5_0!
        Main Boot Mode is 120
        Running the board configuration initialization from R5!
        Happy Debugging!!
        js:> loadJSFile "C:\ti\mcu_plus_sdk_am243x_08_04_00_17\tools\ccs_load\am243x\load_dmsc.js"
        Connecting to DMSC_Cortex_M3_0!
        Fill R5F ATCM memory...
        Writing While(1) for R5F
        Loading DMSC Firmware ... C:/ti/mcu_plus_sdk_am243x_08_04_00_17//source/drivers/sciclient/soc/am64x_am243x/sysfw.bin
        DMSC Firmware Load Done...
        DMSC Firmware run starting now...
        XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

      • and the output of console(including DDR initialization and write_read test) is

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        DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
        DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
        DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
        DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors
        DMSC_Cortex_M3_0: GEL Output: Bootvectors configured.
        DMSC_Cortex_M3_0: GEL Output: Running from DMSC
        DMSC_Cortex_M3_0: GEL Output: Debugging enabled
        DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
        DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
        DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs.
        DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs.
        DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x000003FF
        DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x000003FF
        DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 10
        DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
        DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet
        DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
        DMSC_Cortex_M3_0: GEL Output: For debugging:
        DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
        DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000
        DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000
        XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

      • According to this during running "loadJSFile "C:\ti\mcu_plus_sdk_am243x_08_04_00_17\tools\ccs_load\am243x\load_dmsc.js" DDR initialization got failed as per the below image.

      • So later, i initialized through "scripts->AM64 DDR initialization->AM64_DDR_Initialization_ECC_Disabled", then again i check the DDR status. So its initialized successfully.

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        MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR Initialization completed... <<<---
        MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR4 Initialization is DONE! <<<---
        MAIN_Cortex_R5_0_0: GEL Output: PI Initialization has been triggered.
        MAIN_Cortex_R5_0_0: GEL Output: CTL Initialization has been triggered.
        MAIN_Cortex_R5_0_0: GEL Output: CTL Initialization has been completed.
        MAIN_Cortex_R5_0_0: GEL Output: PI Initialization has been completed.
        MAIN_Cortex_R5_0_0: GEL Output: Starting WrRd Test 1: *wr32_ptr=i
        XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

      • But after that if i will do write_read test through Script, then its failed.

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        MAIN_Cortex_R5_0_0: Data verification failed at 0x80000000 Expected = 0x00000000 Actual= 0xFFFFFFFF
        MAIN_Cortex_R5_0_0: Data verification failed at 0x80000004 Expected = 0x01010101 Actual= 0xFFFFFFFF
        MAIN_Cortex_R5_0_0: GEL Output: Starting WrRd Test 2: *wr32_ptr=~i
        MAIN_Cortex_R5_0_0: Data verification failed at 0x80000000 Expected = 0x030100FF Actual= 0xFFFFFFFF
        MAIN_Cortex_R5_0_0: Data verification failed at 0x80000004 Expected = 0x0100FFFE Actual= 0xFFFFFFFF
        MAIN_Cortex_R5_0_0: GEL Output:
        !!!!! DDR Basic read/write test Failed !!!!
        XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    2. Method-2(Directly running from Script)
      1. When i tried without gel file and initialized directly through script, its unable to initialize and give following error.
    3. Method-3(Initialized though gel and ran direct write_read test)
      1. Initialized the processor through "loadJSFile "C:\ti\mcu_plus_sdk_am243x_08_04_00_17\tools\ccs_load\am243x\load_dmsc.js" and then directly ran the write_read test.

    I have tried with EVM, in that if i follow the method-1 sequence then I am able to run all test successfully. Please note it.

    If i am missing any sequence, then please provide me the initialization sequence. I will try with that.

    Please help me out.

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Guru* 79810 points

    Hi Divyesh, every one of the methods you tried included executing the load_dmsc.js.  Keep this out of the sequence.  Just perform the following:

    -power on board in No Boot mode

    -connect to the board by going to the target configuration for your board and selecting Launch Selected Configuration

    -connect to DMSC.  Gel will run automatically to initialize PLL/PSC

    -connect to Cortex_R5_0_0.  Run GEL script Scripts -> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled

    -run the read/write test

    Regards,

    James

  • 0 in reply to JJD
    Intellectual 765 points

    Hi James,

    PFA recording

    Waiting for your feedback.

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Guru* 79810 points

    Hi DIvyesh, thanks for the video.  You appear to be doing everything as expected.  We need to dig a little deeper.  Can you send the results of Scripts->AM64 DDRSS DEbug -> Memory Debug -> AM64 DDRSS CTL PI PHY RegDump and AM64 DDRSS SS RegDump

    Also can you share the DDR portion of your schematic?

    REgards,

    James

  • 0 in reply to JJD
    Intellectual 765 points

    Hi James,

    Thank you for your support.

    PFA video and log

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    DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
    DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
    DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
    DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors
    DMSC_Cortex_M3_0: GEL Output: Bootvectors configured.
    DMSC_Cortex_M3_0: GEL Output: Running from DMSC
    DMSC_Cortex_M3_0: GEL Output: Debugging enabled
    DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
    DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs.
    DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs.
    DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x000003FF
    DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x000003FF
    DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 10
    DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
    DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet
    DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
    DMSC_Cortex_M3_0: GEL Output: For debugging:
    DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
    DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000
    DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    This log is without DDR initialization.

    I am getting different output, if I initialize DDR through scripts->AM64 DDR initialization->AM64_DDR_Initialization_DDR_Disabled and then run the Scripts->AM64 DDRSS DEbug -> Memory Debug -> AM64 DDRSS CTL PI PHY then output is as below.

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    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR4 Initialization is in progress ... <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> ECC Disabled <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming in progress.. <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming completed... <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming in progress.. <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming completed... <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 0 programming in progress.. <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming in progress.. <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming completed... <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address slice 2 programming in progress.. <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 2 programming completed... <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming in progress.. <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> Set PHY registers for all FSPs simultaneously (multicast)... <<<---
    MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming completed... <<<---
    MAIN_Cortex_R5_0_0: GEL Output: Running from R5 or A53
    MAIN_Cortex_R5_0_0: GEL Output: Debugging enabled
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Guru* 79810 points

    Hi divyesh,

    the register dump is showing that none of the training is completing correctly.  Something is fundamentally wrong.  Can you share your schematics?

    Do you know if the DDR layout guidelines found here:  https://www.ti.com/lit/pdf/spracu1 were followed during board design?

    Regards,

    james

  • 0 in reply to JJD
    Intellectual 765 points

    Hi James,

    Could you please provide your email id? I will mail you schematic.

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Guru* 79810 points

    i sent an email.

    James

  • 0 in reply to JJD
    Intellectual 765 points

    Hi James,

    Thank you for your support.

    I have mailed you.

    Waiting for your feedback.

    --

    Thanks & Regards,

    Divyesh Patel

  • +1 in reply to Divyesh Patel
    TI__Guru* 79810 points

    there are several issues with the schematic which i have detailed in the email

    regards,

    James

  • 0 in reply to JJD
    Intellectual 765 points

    Hi James,

    Thank you for your support.

    I have mailed you my queries, please provide me guidance.

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    Intellectual 765 points

    Hi James,

    PFA image, DDR write/read test is passed.

    Thank you so much for your support and guidance :-)

    --

    Thanks & Regards,

    Divyesh Patel

  • 0 in reply to Divyesh Patel
    TI__Guru* 79810 points

    Divyesh, what was the change to get it to work?

    Regards,

    james

  • 0 in reply to JJD
    Intellectual 765 points

    Hi James,

    In schematic only, that coupling voltage and clock signal voltage. It was coupled with 3.3V instead of VDDS_DDR(1.2V)

    --

    Thanks & Regards,

    Divyesh Patel