AM2434: [AM2434_ALV] System reset (CCS) can not enter the bootloader

Hello,

Could you please share at what point you are doing the warm reset and the code for the same?

Thanks!

Thanks for you reply，The moment we do doing the warm reset at the time of simulation is uncertain and the warm-reset function at runtime is called directly via the RTOS shell.

Hello,

What is the exact SPI primary bootmode you are using?

I am suspecting the ROM is having trouble reading the flash after a warm reset. This may happen if the flash is not getting reset on wam reset and so the ROM gets the flash part in the state left by the bootloader.

Regards,

Prashant

Hello，

We configure bootmode to bit[15:7] =  [0000 1101 0] ,bit[6:0] =  [001 1011], so our primary bootmode is SPI.

The flash we use is GD25Q256 and the communication protocol is 1s-1s-1s，PHY MODE is not enable, Once this mode is used, an error occurs when the SPI communicates with Flash.

In the past few days, we've tried to configure flash's reset function, but it didn't work. why RESETSTATz can't produce a reset signal to #RESET of flash?

I found that the EVM board OSPI (8d-8d-8d) can reset the flash, but my board can't generate a reset signal using 1s-1s-1s.

Do you have any other suggestions?

Best wishes

Hello,

Finally, we solved this problem by modifying the warm reset signal(RESETSTATz).
The cause of the problem is indeed the processing of the flash reset pin, and the flash reset pin has other functions on our board to be multiplexed..
But I have a question is that the reset signal (GPIO_OSPI_RSTn) of the OSPI must be in 8D-8D-8D mode to be generated? This signal was not measured on our board [1S-1S-1S].

Best wishes

Hello Pan Fei,

GPIO_OSPI_RSTn is an alternative reset option that can be used to reset the flash without resetting the SOC.

GPIO_OSPI_RSTn is connected to one of the SOC IO for software control of flash reset.

Pan Fei said:

Finally, we solved this problem by modifying the warm reset signal(RESETSTATz).
The cause of the problem is indeed the processing of the flash reset pin, and the flash reset pin has other functions on our board to be multiplexed.

Are you able to share the schematics to review and comment.

Is there a pullup connected to the flash reset input.

If yes you may have to reconfigure the pullup to pulldown to hold the flash in reset until the SOC reset status is de-asserted.

Regards,

Sreenivasa

Hello Sreenivasa,

The flash in my board is selected to be GD25Q256  with WSON8 package, the reset pin is the hold function by default, it needs to be configured as the reset function through the status register,and the QUAD mode cannot be used, otherwise, this pin will become the data pin of quad communicatio, The above two points are the main reasons why the warm reset goes into UARTmode.

Secondly, my board has a 3.3V pull-up with 10K on RESETSTATz, at first we thought there was a problem with this, we changed it to a pull-down, but later we found that the other board  with pull-up also succeeded.

The schematic is the same as the EVM board except for the pull-up.

Best regards

Panfei

Hello,

Thank you for the reminder, we'll pay attention to this later.

Regards,

Panfei