AM2434: AM2434: EtherCAT device profile Q2

Chockalingam N said:

How is the EtherCAT slave implemented in EtherCAT solution which we got from TI code base?

Hi Chockalingam,

EtherCAT SUbDevice is implemenated on the TI SoCs with PRU-ICSS IP to enable customers add EtherCAT SubDevice protocol support to their system. It implements EtherCAT SubDevice Controller(ESC) Layer 2 functionality with two MII ports (one IN and one OUT port per PRU-ICSS) in accordance with ETG.1000.4 Data Link Layer protocol specification. This provides EtherCAT ASIC like functionality integrated into TI SoCs.

Below shows the architecture diagram for the same: 

hi Nilabh,

As i understood, MII as in 4tx and 4rx pins on per port, one port input and one port output for PRU-ICSS. Due to hardware size constraint, we are planning to reduce the MII to SMII (1tx & 1rx) per port using DP83869HMRGZT (PHY). Will etherCAT, profineti/o and ethernet/IP protocol communication be affected in anyway.

Hi Santosh,

Santosh Sirsi said:

planning to reduce the MII to SMII (1tx & 1rx) per port using DP83869HMRGZT (PHY). Will etherCAT, profineti/o and ethernet/IP protocol communication be affected in anyway.

Hi Santosh,

We only support MII and RGMII with Protocols , 

Thank for the reply, Maybe i did not ask question clearly.

Please see connection the block diagram below and confirm your reply

In the block diagram, Ethernet MAC is a part of AM2434 (with RGMII interface) connected to DP83869HMRGZT (PHY IC) that converts RGMII to SGMII, That is in turn connected to PHY (RJ45)

Will etherCAT, profineti/o and ethernet/IP protocol communication be affected in anyway?

with reference to AM2434 launch E3, we are using DP83869HMRGZT (PHY IC)

1. As per our understanding, for Ethercat,

In the above figure, we were able to figure out that controller MAC is configured in MII mode and as well as PHY DP83869HMRGZT (PHY IC input ) in MII mode. And on other side of DP83869HMRGZT (PHY IC output) it could be SGMII, is that possible in this IC, if yes, will it work for EtherCAT.

For EtherNet/IP and profinet i/o, we can go for RGMII (controller MAC) to RGMII (PHYIC input) and RGMII (PHYIC output) 

below is the code snipet from TI am2434 code base that sets MII mode in DP83869HMRGZT (PHY IC). but could figure the PHY settings for the other side of PHY (output side) in code.

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
void CUST_PHY_DP83869_setMIIMode(void *pAppCtxt_p, void *pStackCtxt_p)
{
    phyRegVal = CUST_PHY_DP83869_readExtendedRegister(pAppCtxt_p, pStackCtxt_p, CUST_PHY_DP83869_OP_MODE_DECODE);
    phyRegVal |= CUST_PHY_DP83869_DATA_OPMODE_DECODE_MII;
    CUST_PHY_DP83869_writeExtendedRegister(pAppCtxt_p, pStackCtxt_p, CUST_PHY_DP83869_OP_MODE_DECODE, phyRegVal);
}

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

2. If we choose to go with dp83822i (PHY IC), it supports MII/RMII/RGMII to SMII. it could work by selecting MII to MII for ethercat and ethernet/ip.

how will it work for profinet i/o IR/IRT - real time data?

Santosh Sirsi said:

In the above figure, we were able to figure out that controller MAC is configured in MII mode and as well as PHY DP83869HMRGZT (PHY IC input ) in MII mode. And on other side of DP83869HMRGZT (PHY IC output) it could be SGMII, is that possible in this IC, if yes, will it work for EtherCAT.

Hi Santosh, Thanks for clarifying this, as stated above if you have MII for EtherCAT MAC then it should work. But please confirm once with the PHY team before going ahead with the design. I do not see a risc from MAC side.

Santosh Sirsi said:

below is the code snipet from TI am2434 code base that sets MII mode in DP83869HMRGZT (PHY IC). but could figure the PHY settings for the other side of PHY (output side) in code.

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
void CUST_PHY_DP83869_setMIIMode(void *pAppCtxt_p, void *pStackCtxt_p)
{
    phyRegVal = CUST_PHY_DP83869_readExtendedRegister(pAppCtxt_p, pStackCtxt_p, CUST_PHY_DP83869_OP_MODE_DECODE);
    phyRegVal |= CUST_PHY_DP83869_DATA_OPMODE_DECODE_MII;
    CUST_PHY_DP83869_writeExtendedRegister(pAppCtxt_p, pStackCtxt_p, CUST_PHY_DP83869_OP_MODE_DECODE, phyRegVal);
}

We do not have SDK support for bridge mode of dp83869 phy, you will need to work with phy team on these details. 

thanks for the reply Nilabh,

can you please help us in connecting to PHY team, arranging a web call would resolve all the queries. From my side FW and HW team would join the call.