AM2631: PLL and clkout pin configuration using SysCfg

Hey Javier,

I am including some example gel code that could be used as a starting point.

Save this source code in a new AM263_CLKOUT_CFG.gel file the GEL directory mentioned in the response above and add the following line with the other gel file calls in the main AM263x.gel file: GEL_LoadGel( "$(GEL_file_dir)/AM263_PLL/AM263_CLKOUT_CFG.gel");

/**
 * \file  AM263_CLKOUT_CONFIG.gel
 *
 * \brief GEL File to configure CLKOUT0 for AM263x
 */

/* Copyright (c) 2024, Texas Instruments Incorporated
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/* Revision history:
 * 02-15-2024 - Initial Creation
 */

// Register Definitions and Offsets
#define IOMUX_U_BASE											(0x53100000U)
#define IOMUX_IO_CFG_KICK0										(0x00000298U)
#define IOMUX_IO_CFG_KICK1								 		(0x0000029CU)
#define IOMUX_CLKOUT0_CFG_REG									(0x00000228U)
#define IOMUX_SDFM0_CLK0_CFG_REG								(0x000001E8U)

#define MSS_TOP_RCM_U_BASE										(0x53200000U)
#define MSS_TOP_RCM_LOCK0_KICK0									(0x00001008U)
#define MSS_TOP_RCM_LOCK0_KICK1									(0x0000100CU)

#define MSS_TOP_RCM_CLKOUT0_CLK_SRC_SEL							(0x00000C00U)
#define MSS_TOP_RCM_CLKOUT1_CLK_SRC_SEL							(0x00000C04U)
#define MSS_TOP_RCM_CLKOUT0_DIV_VAL								(0x00000C08U)
#define MSS_TOP_RCM_CLKOUT1_DIV_VAL								(0x00000C0CU)
#define MSS_TOP_RCM_CLKOUT0_CLK_GATE							(0x00000C10U)
#define MSS_TOP_RCM_CLKOUT1_CLK_GATE							(0x00000C14U)
#define MSS_TOP_RCM_CLKOUT0_CLK_STATUS							(0x00000C18U)
#define MSS_TOP_RCM_CLKOUT1_CLK_STATUS							(0x00000C1CU)

#define XTALCLK													(0x000)
#define DPLL_CORE_HSDIV_CLKOUT0									(0x111)
#define DPLL_CORE_HSDIV_CLKOUT1									(0x222)
#define DPLL_PER_HSDIV_CLKOUT0									(0x333)
#define DPLL_PER_HSDIV_CLKOUT1									(0x444)
#define RCCLK10M												(0x555)
#define RCCLK32K												(0x666)
#define CPTS_GENF0												(0x777)

#define div1													(0x000)
#define div2													(0x111)
#define div3													(0x222)
#define div4													(0x333)
#define div5													(0x444)
#define div6													(0x555)
#define div7													(0x666)
#define div8													(0x777)
#define div9													(0x888)
#define div10													(0x999)
#define div11													(0xAAA)
#define div12													(0xBBB)
#define div13													(0xCCC)
#define div14													(0xDDD)
#define div15													(0xEEE)
#define div16													(0xFFF)


hotmenu Make_CLKOUT0_25MHz_XTALCLK_div1() 
{
	MSS_TOPRCM_unlock();

	// Use CLK Source defines as the input source clock for CLKOUT0
	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_CLK_SRC_SEL, XTALCLK);
	GEL_TextOut("XTALCLK selected as CLK source for CLKOUT0\n");
	
	// Write DIV_VAL as the clock divider value for CLKOUT0
	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_DIV_VAL, div1);
	GEL_TextOut("XTALCLK will be divided by 0 for 25MHz CLKOUT0\n");
}


hotmenu Make_CLKOUT0_10MHz_RCCLK10M_div1() 
{
	MSS_TOPRCM_unlock();

	// Use CLK Source defines as the input source clock for CLKOUT0
	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_CLK_SRC_SEL, RCCLK10M);
	GEL_TextOut("RCCLK10M selected as CLK source for CLKOUT0\n");
	
	// Write DIV_VAL as the clock divider value for CLKOUT0
	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_DIV_VAL, div1);
	GEL_TextOut("RCCLK10M will be divided by 1 for 10MHz CLKOUT0\n");
}


hotmenu Make_CLKOUT0_5MHz_RCCLK10M_div2() 
{
	MSS_TOPRCM_unlock();

	// Use CLK Source defines as the input source clock for CLKOUT0
	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_CLK_SRC_SEL, RCCLK10M);
	GEL_TextOut("RCCLK10M selected as CLK source for CLKOUT0\n");
	
	// Write DIV_VAL as the clock divider value for CLKOUT0
	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_DIV_VAL, div1);
	GEL_TextOut("RCCLK10M will be divided by 2 for 5MHz CLKOUT0\n");
}


hotmenu Make_CLKOUT0_2MHz_RCCLK10M_div5() 
{
	MSS_TOPRCM_unlock();

	// Use CLK Source defines as the input source clock for CLKOUT0
	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_CLK_SRC_SEL, RCCLK10M);
	GEL_TextOut("RCCLK10M selected as CLK source for CLKOUT0\n");
	
	// Write DIV_VAL as the clock divider value for CLKOUT0
	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_DIV_VAL, div5);
	GEL_TextOut("RCCLK10M will be divided by 5 for 2MHz CLKOUT0\n");
}


hotmenu Make_CLKOUT0_32kHz_RCCLK32_div1() 
{
	MSS_TOPRCM_unlock();

	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_CLK_SRC_SEL, RCCLK32K);
	GEL_TextOut("RCCLK32K selected as CLK source for CLKOUT0\n");
	
	// Write DIV_VAL as the clock divider value for CLKOUT0
	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_DIV_VAL, div1);
	GEL_TextOut("RCCLK32K will be divided by 1 for 32kHz CLKOUT0\n");
}


hotmenu Make_CLKOUT0_16kHz_RCCLK32K_div2() 
{
	MSS_TOPRCM_unlock();

	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_CLK_SRC_SEL, RCCLK10M);
	GEL_TextOut("RCCLK32K selected as CLK source for CLKOUT0\n");
	
	// Write DIV_VAL as the clock divider value for CLKOUT0
	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_DIV_VAL, div2);
	GEL_TextOut("RCCLK32K will be divided by 2 for 16kHz CLKOUT0\n");
}


hotmenu Make_CLKOUT0_8kHz_RCCLK32K_div4() 
{
	MSS_TOPRCM_unlock();

	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_CLK_SRC_SEL, RCCLK32K);
	GEL_TextOut("RCCLK32K selected as CLK source for CLKOUT0 \n");
	
	// Write DIV_VAL as the clock divider value for CLKOUT0
	Write_MMR(MSS_TOP_RCM_U_BASE+ MSS_TOP_RCM_CLKOUT0_DIV_VAL, div4);
	GEL_TextOut("RCCLK32K will be divided by 4 for 8kHz CLKOUT0\n");
}

Hope this helps!

Best Regards,

Zackary Fleenor