Part Number: TMS570LC4357
Hi
I'm encountering an unexpected behavior while transitioning from a bootloader to a Real-Time Operating System (RTOS) application on the TMS570LC43x microcontroller. Specifically, when jumping from the bootloader code to the RTOS application, the processor's Program Counter (PC) seems to enter an SVC (Supervisor Call) entry instead of directly executing the application code.
Details:
- Microcontroller: TMS570LC43x
- Bootloader: Custom bootloader code based on UART, (build upon the TI Bootloader)
- RTOS: FOXBMS Code using Free RTOS .
- Development Environment: Code Composer Studio (CCS) for Bootloader , VS code for Application.
- Observation: Upon transition from the bootloader to the RTOS application, the PC enters an SVC entry point instead of directly executing the application code.
Questions:
- What could be causing the processor to enter the SVC entry upon transitioning from the bootloader to the RTOS application?
- Is it normal behavior for an RTOS application to begin execution from an SVC entry point, or does this indicate a potential issue in the application or bootloader setup?
- How can I verify that the RTOS initialization routine is being called correctly and that subsequent application tasks are executed as expected?
- Are there any specific configuration settings or startup sequence considerations I should be aware of when transitioning from a bootloader to an RTOS application on the TMS570LC43x microcontroller?
- Are there any debugging techniques or tools I can use to trace the execution flow and diagnose the cause of the unexpected SVC entry during the transition?
Linker files & .intvecs file is attached.
Bootloader CMD FILE
/*----------------------------------------------------------------------------*/
/* sys_link.cmd */
/* */
/*----------------------------------------------------------------------------*/
/* Linker Settings */
--retain="*(.intvecs)"
/* USER CODE BEGIN (1) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/
/* Memory Map */
MEMORY
{
/* USER CODE BEGIN (2) */
#if 0
/* USER CODE END */
VECTORS (X) : origin=0x00000000 length=0x00000020
FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0
FLASH1 (RX) : origin=0x00200000 length=0x00200000
STACKS (RW) : origin=0x08000000 length=0x00000800
RAM (RW) : origin=0x08000800 length=0x0007f800
/* USER CODE BEGIN (3) */
#endif
#if 1
VECTORS (X) : origin=0x00000000 length=0x00000020 fill = 0xffffffff
FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0 vfill = 0xffffffff
FLASH1 (RX) : origin=0x00200000 length=0x00200000 vfill = 0xffffffff
/* Bank 7 (128kB, FEE) */
FLASH7 (R) : origin=0xF0200000 length=0x00020000 vfill = 0xffffffff
STACKS (RW) : origin=0x08000000 length=0x00001500
RAM (RW) : origin=0x08001500 length=0x0002EB00
/* Bank 0 ECC */
ECC_VEC (R) : origin=(0xf0400000 + (start(VECTORS) >> 3))
length=(size(VECTORS) >> 3)
ECC={algorithm=algoL2R5F021, input_range=VECTORS}
ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0) >> 3))
length=(size(FLASH0) >> 3)
ECC={algorithm=algoL2R5F021, input_range=FLASH0 }
/* Bank 1 ECC */
ECC_FLA1 (R) : origin=(0xf0400000 + (start(FLASH1) >> 3))
length=(size(FLASH1) >> 3)
ECC={algorithm=algoL2R5F021, input_range=FLASH1 }
/* Bank 7 ECC */
ECC_FLA7 (R) : origin=0xF0100000
length=(size(FLASH7) >> 3)
ECC={algorithm=algoL2R5F021, input_range=FLASH7 }
#endif
/* USER CODE END */
}
/* USER CODE BEGIN (4) */
#if 1
ECC {
algoL2R5F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */
hamming_mask = R4 /* Use R4/R5 build in Mask */
parity_mask = 0x0c /* Set which ECC bits are Even and Odd parity */
mirroring = F021 /* RM57Lx and TMS570LCx are build in F021 */
}
#endif
/* USER CODE END */
/*----------------------------------------------------------------------------*/
/* Section Configuration */
SECTIONS
{
/* USER CODE BEGIN (5) */
#if 0
/* USER CODE END */
.intvecs : {} > VECTORS
.text align(32) : {} > FLASH0 | FLASH1
.const align(32) : {} > FLASH0 | FLASH1
.cinit align(32) : {} > FLASH0 | FLASH1
.pinit align(32) : {} > FLASH0 | FLASH1
.bss : {} > RAM
.data : {} > RAM
.sysmem : {} > RAM
/* USER CODE BEGIN (6) */
#endif
#if 1
.intvecs : {} palign=8 > VECTORS
flashAPI:
{
.\source\Fapi_UserDefinedFunctions.obj (.text, .data)
.\source\bl_flash.obj (.text, .data)
--library = F021_API_CortexR4_BE_L2FMC.lib (.text, .data)
} palign=8 load = FLASH0 |FLASH1, run = RAM, LOAD_START(apiLoadStart), RUN_START(apiRunStart), SIZE(apiLoadSize)
.text : {} palign=8 > FLASH0 |FLASH1
.const : {} palign=8 load=FLASH0 |FLASH1
.cinit : {} palign=8 > FLASH0 | FLASH1
.pinit : {} palign=8 > FLASH0 | FLASH1
.bss : {} > RAM /* Uninitialized global and static variables */
.data : {} > RAM /* Global and static non-const variables that are explicitly initialized. */
.sysmem : {} > RAM /* Memory pool (heap) for dynamic memory allocation */
#endif
/* USER CODE END */
}
/* USER CODE BEGIN (7) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/
/* Misc */
/* USER CODE BEGIN (8) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/
Bootloader HL_sys_intvecs.asm
; HL_sys_intvecs.asm
.sect ".intvecs"
.arm
;-------------------------------------------------------------------------------
; import reference for interrupt routines
.ref _c_int00
.ref phantomInterrupt
.def resetEntry
;-------------------------------------------------------------------------------
; interrupt vectors
resetEntry
b _c_int00
undefEntry
b undefEntry
svcEntry
b svcEntry
prefetchEntry
b prefetchEntry
dataEntry
b dataEntry
b phantomInterrupt
ldr pc,[pc,#-0x1b0]
ldr pc,[pc,#-0x1b0]
;-------------------------------------------------------------------------------
Application CMD File
1.linker_script_elf.cmd
linker_script_elf.cmd
* never remove intvecs during linking */
--retain="*(.intvecs)"
/*========== TMS570LC43xx Memory Map ========================================*/
/* docref: SPNS195C - FEBRUARY 2014 - REVISED JUNE 2016
* TMS570LC4357 Hercules™ Microcontroller Based on the ARM® Cortex®-R Core SPNS195C
* 6.9.1 Memory Map Diagram (Page 90)
* - Figure 6-9. Memory Map: Flash ECC, OTP and EEPROM accesses) from 0xF000 0000 to 0xF047 FFFF
* 6.9.2 Memory Map Table (Page 91)
* - Table 6-25. Module Registers / Memories Memory Map:
* Flash Data Space ECC start: 0xF040 0000
* Flash Data Space ECC end: 0xF05F FFFF (but only usable till 0xF047 FFFF, see also memory map)
*/
/* size of flash banks in TMS570LC43xx */
#define FLASH_BANK_SIZE (0x200000)
/* global size of the FLASH memory in the MCU (TMS570LC43xx has 2 flash banks) */
#define GLOBAL_FLASH_SIZE (1 * FLASH_BANK_SIZE)
#define FLASH_BANK0_START_ADDRESS (0x00000000)
#define FLASH_BANK0_END_ADDRESS (0x001FFFFF)
#define FLASH_BANK1_START_ADDRESS (0x00200000)
#define FLASH_BANK1_END_ADDRESS (0x003FFFFF)
/* Data ECC area: 0xF0400000 to 0xF0480000 */
#define ECC_DATA_START_ADDRESS (0xF0400000)
/* start address of the vectors table in ARM (if not otherwise defined, i.e., during flashing) */
#define VECTORS_TABLE_START_ADDRESS (0x00200000) /*(0x00020000)*//*(0x00000000)*/
/* size of RAM in TMS570LC43xx */
#define GLOBAL_RAM_SIZE (0x80000)
/* global start address of RAM in TMS570LC43xx */
#define GLOBAL_RAM_START_ADDRESS (0x08000000)
/*========== Flash section configuration ====================================*/
#define VFILL_FLASH_PATTERN (0xffffffff)
/* size of VER_VERSION_INFORMATION (has to be large enough to accomodate the version struct) */
#define VERSION_INFORMATION_SIZE (0xC0)
/* size of the VECTORS table */
#define VECTORS_TABLE_SIZE (0x20)
/* size of KERNEL (accomodates the OS) */
#define KERNEL_FUNCTIONS_SIZE (0x8000)
/* remaining size of flash bank 0 as at the beginning of flash bank 0 the vector
* table and version information struct are placed 0x1D7F20*/
#define REMAINING_FLASH_BANK0_SIZE (FLASH_BANK_SIZE - VECTORS_TABLE_SIZE - KERNEL_FUNCTIONS_SIZE - VERSION_INFORMATION_SIZE )*/
/* program usable flash size is "remaining flash bank0 size + complete flash bank 1 size" */
#define FLASH_SIZE (0x001F7F1F)
/*========== ECC Flash section configuration ================================*/
/* sizes for ECC */
#define ECC_VECTORS_TABLE_SIZE (VECTORS_TABLE_SIZE/8)
#define ECC_KERNEL_FUNCTIONS_SIZE (KERNEL_FUNCTIONS_SIZE/8)
#define ECC_FLASH_SIZE (FLASH_SIZE/8)
#define ECC_VERSION_INFORMATION_SIZE (VERSION_INFORMATION_SIZE/8)
/*========== RAM section configuration ======================================*/
/* The size of the stacks has to be exactly the same as DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE from HalCoGen! */
/* The stack consists of:
* - user stack
* - supervisor stack
* - FIQ stack (FIQ: fast interrupt)
* - IRQ stack (IRQ: normal interrupt)
* - Abort stack
* - Undefined stackarm-none-eabi-objcopy -I binary -O ihex foxbms.bin output.hex
*/
#define STACKS_SIZE (0x800)
/* size of the FreeRTOS RAM; TODO does this have to fit to another value? */
#define KERNEL_DATA_SIZE (0x800)
/* size of shared-RAM section for DMA */
#define SHARED_RAM_SIZE (0x2000)
/*========== Memory Layout ==================================================*/
MEMORY
{
/* FLASH */
VECTORS_TABLE (X) : origin = 0x00200000
length = 0x20
vfill = VFILL_FLASH_PATTERN
KERNEL_FUNCTIONS (RX) : origin = 0x00200020
length = 0x8000
vfill = VFILL_FLASH_PATTERN
FLASH (RX) : origin = 0x00208020
length = 0x0001B7F20
vfill = VFILL_FLASH_PATTERN
VER_VERSION_INFORMATION (RX) : origin = 0x003BFF40
length = 0xC0
vfill = VFILL_FLASH_PATTERN
/* RAM */
STACKS (RW) : origin = GLOBAL_RAM_START_ADDRESS
length = STACKS_SIZE
KERNEL_DATA (RW) : origin = end(STACKS)
length = KERNEL_DATA_SIZE
RAM (RW) : origin = end(KERNEL_DATA)
length = (GLOBAL_RAM_SIZE - STACKS_SIZE - KERNEL_DATA_SIZE - SHARED_RAM_SIZE)
SHARED_RAM (RW) : origin = end(RAM)
length = SHARED_RAM_SIZE
ECC_VECTORS_TABLE (R) : origin = ECC_DATA_START_ADDRESS
length = ECC_VECTORS_TABLE_SIZE
ECC = { input_range = VECTORS_TABLE }
ECC_KERNEL_FUNCTIONS (R) : origin = end(ECC_VECTORS_TABLE)
length = ECC_KERNEL_FUNCTIONS_SIZE
ECC = { input_range = KERNEL_FUNCTIONS }
ECC_FLASH (R) : origin = end(ECC_KERNEL_FUNCTIONS)
length = ECC_FLASH_SIZE
ECC = { input_range = FLASH }
ECC_VERSION_INFORMATION (R) : origin = end(ECC_FLASH)
length = ECC_VERSION_INFORMATION_SIZE
ECC = { input_range = VER_VERSION_INFORMATION }
}
/*========== ECC Algorithm Configuration ====================================*/
ECC
{
algo_name : address_mask = 0xfffffff8
hamming_mask = R4
parity_mask = 0x0c
mirroring = F021
}
/*========== Section Layout =================================================*/
SECTIONS
{
.intvecs : {} > VECTORS_TABLE
/* FreeRTOS Kernel in protected region of Flash */
.kernelTEXT align(32) : {} > KERNEL_FUNCTIONS
.cinit align(32) : {} > KERNEL_FUNCTIONS
/* Rest of code to user mode flash region */
.versionInformation align(32) : {} > VER_VERSION_INFORMATION
.syscallTEXT align(32) : {} > FLASH
.text align(32) : {} > FLASH
.const align(32) : {} > FLASH
/* FreeRTOS Kernel data in protected region of RAM */
.kernelBSS : {} > KERNEL_DATA
.bss : {} > RAM
.data : {} > RAM
.sysmem : {} > RAM
.sharedRAM : {} > SHARED_RAM
}
2.linker_script_hex.cmd
/*linker_script_hex.cmd*/
/* Aligned with names in "MEMORY" in the elf-linker script */
ROMS
{
/* FLASH */
VECTORS_TABLE : origin = 0x00200000/*0x00020000*//*0x00000000*/
length = 0x20
fill = 0xFFFFFFFF
KERNEL_FUNCTIONS : origin = 0x00200020
length = 0x8000
fill = 0xFFFFFFFF
FLASH : origin = 0x00208020 /*(0x00000000 + 0x20 + 0x8000)*/
length = 0x0001B7F20 /*0x3F7F20 //3D 7F20 1966034 */
fill = 0xFFFFFFFF
VER_VERSION_INFORMATION : origin = 0x003BFF40 /*0x0001FFF40 *//*0x003FFF40(0x00000000 + 0x20 + 0x8000 + 0x3F7F20) // arj*32 FF40/ 0x003FFF40*/
length = 0xC0
fill = 0xFFFFFFFF
/* RAM */
STACKS : origin = 0x08000000
length = 0x800
KERNEL_DATA : origin = 0x08000800
length = 0x800
RAM : origin = 0x08001000
length = 0x7D000
SHARED_RAM : origin = 0x0807E000
length = 0x2000
ECC_VECTORS_TABLE : origin = 0xF0400000
length = 0x4
ECC_KERNEL_FUNCTIONS : origin = 0xF0400004
length = 0x1000
ECC_FLASH : origin = 0xF0401004
length = 0x7EFE4
ECC_VERSION_INFORMATION : origin = 0xF047FFE8
length = 0x18
}
Any insights or guidance on resolving this issue would be greatly appreciated. Thank you!
