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Original question:

AM2632: PBIST / testable memory regions

AM2632: AM2632: PBIST / testable memory regions

Jo Scho
Intellectual 300 points
Part Number: AM2632


Hello, 

I opened a related thread, because my other thread to this topic is already closed.

Here the link to the original thread: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1301037/am2632-pbist-testable-memory-regions?tisearch=e2e-sitesearch&keymatch=pbist#

I try to setup a functional safety application, which uses R5SS0 on AM2632, in lockstep mode.
To achieve our safety goals, my application needs a stuckAt-memory test, which I want to realize with pBIST-Library from the SDK.
I still have some comprehension problems with the testable memory regions.

In the thread, mentioned above,  said. that the ROM loader (RBL) already tests some memory region, unfortunately the mentioned memory areas are not corresponding with the technical reference manual...

Is the manual wrong or the statement of Vishwanath Reddy?

 

Then my next question is about the TCM namings. What is the CR5A and CR5B standing for? 

Is "CR5A" and "CR5B" another  naming for the cores? (core 0 and core 1)


And what is ATCM and BTCM? I tried to match it with the block diagram in the technical user manual, but I failed... is the TCM of one core separated into four sections (ATCM0, ATMC1 and BTMC0 and BTMC1)...

Another memory naming, I have found in the SDL library is R5SS0 RAM and R5SS1 RAM, what memory is this (adress area?)?

Best regards

Jo Scho