AM2432: FSI CLK 50MHz Not Match Time Series Requirement

Hello Kevin

Thank you for the query.

Let me review the inputs and check with the expert internally and come back.

Regards,

Sreenivasa

Hi Sreenivasa,

Thanks!

The condition of the above calculation is when clocking frequency = 50MHz, and two-sided edge sampling = 100Mbps.

From the result of the calculation we found that time sequence requirement below might not be meet.

tSU(min)<tW(min)-tD(max)

We also see there is some application note that introduces offset compensation, would this be used to achieve the time series requirement?

Thanks a lot!

Kevin

Hello Kevin

Thank you.

Is there a use case to calculate the timing using the input timing and the output timing of the SOC.

I guess the timing should include the attached device.

Any idea on the attached device.

Regards,

Sreenivasa

Hi Sreenivasa,

The use case is shown below. Two AM243x uses FSI to transmit the data.

The clocking frequency is 50MHz and the transmission speed is 100MHz.

Thanks,

Kevin

hello Kevin,

Thank you for the inputs.

Let me check with the team and update.

Regards,

Sreenivasa

Hi Sreenivasa,

May I know is there any update so far? Please let us know if you need any further clarification, thanks!

Kevin

Hello Kevin, 

Please refer below inputs i received 

Kevin Peng said:

The use case is shown below. Two AM243x uses FSI to transmit the data.

The clocking frequency is 50MHz and the transmission speed is 100MHz.

In this case, they would need to perform a timing analysis taking into account the AM64x switching characteristics, the AM64x timing requirements, and their actual PCB board trace delays to determine the max operating frequency allowed to provide enough margin for the minimum setup/hold requirements.

Regards,

Sreenivasa

Hi Sreenivasa,

The AM64x here could also refer to TDA4 if customer is using TDA4 + AM24 ?

Thanks,

Kevin

Hello Kevin, 

Thank you.

Kevin Peng said:

The AM64x here could also refer to TDA4 if customer is using TDA4 + AM24 ?

Please elaborate the query.

If the question is can the Am64x be replaced by TDA4, i suspect if TDA4 has FSI interface.

https://www.ti.com/lit/ds/symlink/tda4vm.pdf

Regards,

Sreenivasa

Hi Sreenivasa,

Customer is using TDA4 + AM24 already, not AM64 + AM24, so based on your previous AM64x switching characteristics, it also means it depends on the maximum TDA4 switching characteristics could reach?

In summary, whether AM24 could support FSI CLK 50MHz or not, it depends on the master device (AM64x or TDA4) right?

Thanks,

Kevin 

Hello Kevin, 

Thank you.

Kevin Peng said:

In summary, whether AM24 could support FSI CLK 50MHz or not, it depends on the master device (AM64x or TDA4) right?

Your understanding is correct.

Regards,

Sreenivasa

Hi Sreenivasa,

I have confirmed from the customer, we misunderstood this question. The question is under the condition of AM24x self-transmit & self received, whether or not there is possibility of having time series problem when FSI CLK is 50MHz. Customer does not agree with our previous explanation, as they do not think this question has relationship with master device AM64x or TDA4x.

The reason for asking this is from the datasheet we can calculate below.

tSU_min (3ns)  is greater than [tW_rxclk_min (0.5*20 - 1 = 9) -Td_max (0.25*20+2.5 = 7.5) = 1.5ns] 

Could you help check this point please, if our calculation is wrong, please also point it out.

Thanks!

Kevin

Hello Kevin, 

Thank you.

The need for customer to perform the timing analysis and configure the interface speed  is recommended in case of loopback also.

Regards,

Sreenivasa