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Original question:

TMS570LS1224: ECC usage with EEPROM Emulation FEE

TMS570LS1224: FEE ECC Selftest triggering ESM notification

Jens Benner
Intellectual 330 points
Part Number: TMS570LS1224

Tool/software:

Hello Jagasish,

I need to come back to this topic. I use the EEPROM Secors of the TMS570LS1224 as EEPROM Emulation useing my own wear leveinig Algorithm for man years now and it works fine so far. Now I want to EEC feature to get an ESM exception when the FEE gets corrupted.

Therefore I alredy use the Fapi_AutoEccGeneration mode and Multible of 8 Bytes for wehn writing to the FEE.

Fapi_issueProgrammingCommand((uint32_t*)u32_Addr, &(u8_Buffer[0]), u8_idx, NULL, 0, Fapi_AutoEccGeneration)

I configured the ESM like this:

Now I tried to enable the ECC Error detection

    Fapi_FmcRegistersType* p_FmcRegisters = F021_CPU0_BASE_ADDRESS;

    p_FmcRegisters->EeCtrl2.EE_CTRL2_BITS.EE_SEC_THRESHOLD = 1;

    p_FmcRegisters->EeCtrl1.EE_CTRL1_BITS.EE_EDACMODE = 0x05;    // Detection only mode
    p_FmcRegisters->EeCtrl1.EE_CTRL1_BITS.EE_EOFEN    = 1;         // An ESM group 1 channel 35 event will be generated on
                                                                // a single bit error when a one reads as a zero and is corrected
    p_FmcRegisters->EeCtrl1.EE_CTRL1_BITS.EE_EZFEN      = 1;        // An ESM group 1 channel 35 event will be generated on
                                                                //a single bit error when a zero reads as a one and is corrected
    p_FmcRegisters->EeCtrl1.EE_CTRL1_BITS.EE_PEN      = 1;        // Error profiling is enabled.
                                                                // An ESM group 1 channel 35 event will be generated when number
                                                                // of correctable bit errors detected and corrected has reached
                                                                // the threshold value defined in the EE_CTRL2 register.
    p_FmcRegisters->EeCtrl1.EE_CTRL1_BITS.EE_ALL1_OK  = 1;        // Reading of an erased location (64 data bits and the corresponding
                                                                // 8 ECC bits are all ones) will NOT generate ECC errors.
                                                                // The error counter for profiling will NOT increment if
                                                                // all ones are detected.
    p_FmcRegisters->EeCtrl1.EE_CTRL1_BITS.EE_EDACEN   = 0x0a;    // Error Detection and Correction is enabled

and try to trigger an ESM exception with the help of the Hercules Safety_Lib:

    SL_SelfTest_Result fee_stResult;
    bool b_Result = false;

    b_Result = SL_SelfTest_FEE (FEE_ECC_TEST_MODE_1BIT_FAULT_INJECT, false, &fee_stResult);
    b_Result = SL_SelfTest_FEE (FEE_ECC_TEST_MODE_2BIT_FAULT_INJECT, false, &fee_stResult);

The call of SL_SelfTest_FEE() returns true, but the fee_stResult is ST_FAIL and I do not get an ESM exception.

What do I miss?

Kind Regards
Jens

 

  • 0
    TI__Guru 69891 points

    Hi Jens,

    I started working on your issue and will provide you my update ASAP.

    --
    Thanks & Regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    TI__Guru 69891 points

    Hi Jens,

    I don't have LS1224 board so i created a test project similar to yours on my RM46 board and here are my findings:

    Jens Benner said:
    but the fee_stResult is ST_FAIL and I do not get an ESM exception.

    You are right about this, the reason for this is 

    In diagnostic code, only in the case of test type FEE_ECC_TEST_MODE_2BIT or FEE_ECC_TEST_MODE_1BIT they are verifying the error flags and making the fee_stResult as ST_PASS

    But in the case of either FEE_ECC_TEST_MODE_2BIT_FAULT_INJECT or FEE_ECC_TEST_MODE_1BIT_FAULT_INJECT they are directly going into the else statement and making the fee_stResult  as ST_FAIL. I don't know exactly why they are doing this.

    Apart from this status my observation regarding FEE_ECC_TEST_MODE_1BIT_FAULT_INJECT and FEE_ECC_TEST_MODE_2BIT_FAULT_INJECT  tests are

    FEE_ECC_TEST_MODE_2BIT_FAULT_INJECT test working without any issue i mean i was above to get the interrupt also for this test. I am attaching my code for your reference, please verify it.

    The reason i am suspecting for not working in your case is that maybe you are not calling below highlighted lines.

    and also remember that ESM is an FIQ interrupt not IRQ so to enable this FIQ interrupt we should call the _enable_interrupt_ function, if we call the _enable_IRQ then only IRQ interrupt will get enabled not FIQ. So please make sure this.

    And i also find that FEE_ECC_TEST_MODE_1BIT_FAULT_INJECT is not working properly, i mean i am not getting any interrupt for this and also ESM1.35 flag also not setting. But my observation is that it is correcting the single bit properly but not setting the status. I am verifying this and i will try to provide further updates on this.

    Meanwhile you can refer my code:

    FEE_ECC_Errors_TEST_RM46_New.zip

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Intellectual 330 points

    Hello Jagadish,

    thank you very much for your quick response. I now also getting the interrupt for the FEE_ECC_TEST_MODE_2BIT_FAULT_INJECT. 

    Waiting for your information about the FEE_ECC_TEST_MODE_1BIT_FAULT_INJECT.

    Best Regards,
    Jens

  • 0 in reply to Jens Benner
    TI__Guru 69891 points

    Hi Jens,

    Jens Benner said:
    thank you very much for your quick response. I now also getting the interrupt for the FEE_ECC_TEST_MODE_2BIT_FAULT_INJECT. 

    Good to hear that.

    Jens Benner said:
    Waiting for your information about the FEE_ECC_TEST_MODE_1BIT_FAULT_INJECT.

    I will check this.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    TI__Guru 69891 points

    Hi Jens,

    Jens Benner said:
    Waiting for your information about the FEE_ECC_TEST_MODE_1BIT_FAULT_INJECT.

    I did debug the issue today.

    But i could not find any issue in our code, and i am doing exactly in the same as FEE_ECC_TEST_MODE_2BIT_FAULT_INJECT, but don't understand why it is not triggering the interrupt. I made sure our FIQ interrupt in VIM was enabled and i also made sure that single bit interrupt enables in the ESM module. But still the interrupt is not triggering.

    I am suspecting it might be a hardware issue within the controller.

    So, what i want to do is that i want to test in other boards to verify whether this interrupt is triggering or not.

    --
    Thanks & Regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Intellectual 330 points

    Hello Jagadish,

    any news on this issue?

    Kind regards,
    Jens

  • 0 in reply to Jens Benner
    TI__Guru 69891 points

    Hi Jens,

    Apologies for the delay, after my response i didn't get a chance to work on it again.

    I will try again this week and will try to provide you an update by end of this week.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    TI__Guru 69891 points

    Hi Jens,

    I understood the root cause for the issue.

    If you refer the highlighted statement below:

    To trigger the ESM error for single bit flash errors, we should need to set the profiling. If we didn't set the profiling, then there won't be any ESM error for single bit flash error.

    So, i did the following modification in my code:

    For single bit errors case i just enable the Error profiling and also i set the single bit error threshold as 1(that means even one single bit error should need to trigger the ESM module).

    After doing this modification here is the result for diagnostic run for single bit error.

    As you can see ESM 1.35 flag got set, this is nothing but correctable error in flash bank-7.

    I am attaching my modified code for your reference:

    5756.FEE_ECC_Errors_TEST_RM46_New.zip

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Intellectual 330 points

    Hello jagadish,

    Thank you very much. I am getting now notifcations for both, single and double selftest. So wit that can I be sure that I will get these notification with real FEE ECC errors?

    Kind Regards
    Jens

  • +1 in reply to Jens Benner
    TI__Guru 69891 points

    Hi Jens,

    Jens Benner said:
    Thank you very much. I am getting now notifcations for both, single and double selftest. So wit that can I be sure that I will get these notification with real FEE ECC errors?

    You need to make sure one more additional thing:

    You need to make sure the enable of "EEPROM Emulation Error Detection and Correction Enable (EE_EDACEN)".

    As you can see the default value for this is 0x5 that means disable but it should be enabled to trigger FEE ECC errors. This is not required for FEE diagnostic, but it is required to enable for to detect actual FEE ECC errors.

     --
    Thanks & Regards,
    Jagadish.