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AM2732: mibspi read TJA1145 faild

Part Number: AM2732

Tool/software:

HI:

    we use the demo project of  mibspi_loopback_dma_am273x-evm_r5fss0-0_freertos_ti-arm-clang to cfg the TJA1145 cantrancv.

    comment the code  status = MIBSPI_enableLoopback(gMibspiHandle[CONFIG_MIBSPI0],loopback); to disable loopback function

    and we find the TX and RX data right on the spi miso and mosi bus.but err in RXSRAM.

    Another experiment do not comment the code  status = MIBSPI_enableLoopback(gMibspiHandle[CONFIG_MIBSPI0],loopback); enable loopback function,the RXSRAM data is right.

    in addition ,the e2e case about pmic I request before. use the same demo project and the spi used as mibspib, it's useful.

   chang the Macro definitions and variables as follows:


#define APP_MIBSPI_MSGSIZE 10

uint16_t gMibspiTxBuffer1[APP_MIBSPI_MSGSIZE];
uint16_t gMibspiRxBuffer[APP_MIBSPI_MSGSIZE];

uint16_t gMibspiTxBuffer[]=
{
// 0x03ff, // Reg 1 Mode control
0x1400, // Reg:0x0A Lock control. Spi write access enable
0x0207, // Reg 1 Mode control
0x03ff, // Reg 1 Mode control
0x03ff, // Reg 1 Mode control
0x0204, // Reg 1 Mode control
0x03ff, // Reg 1 Mode control
0x03ff, // Reg 1 Mode control
0x0207, // Reg 1 Mode control
0x03ff, // Reg 1 Mode control
0x03ff, // Reg 1 Mode control
};

memory:

syscfg :

spi bus:

 

3Q.

  • Hi:

    Thanks for reaching out to e2e. I contacted my colleague about this issue. In the meantime, can you please provide the following:

    - It sounds like the issue is that the macro changes are not working on TJA1145, is this correct?

    - Do you have a link for the following e2e?

      in addition ,the e2e case about pmic I request before.

    Best,

    Haley

  • Hi:

         “ It sounds like the issue is that the macro changes are not working on TJA1145, is this correct?“

           It doesn't seem to have anything to do with the peripheral chip, the miso mosi  data captured on spi bus  is right. as the picture i showed earlier.

           "Do you have a link for the following e2e?"

           LP876242-Q1: ESM cfg - Power management forum - Power management - TI E2E support forums

          Both use spi dma mode , the main difference is that this time used spiA . Last time it was spiB,

  • HI Haley :

        how is it going。

    BR,

    ZDD

  • Hi ZDD,

    The behaves you observed on the TX RX data lines and TX/RX data buffers are expected.

    1. In the case of the loopback enabled, the TX data immediately comes back to the RX line, so the TX and RX data buffers are the same.

    2. In the case of the loopback disabled, when the first MIBSPI_transfer() is executed, the TX data buffer goes to TJA1145, the RX data buffer is the whatever sent from TJA1145 (it could be garbage this time). The TX and RX data buffers should be different, unless you did the external loopback on TJA1145. Do you know what data are expecting from the TJA1145? If yes, the RX data buffer should match with the expected data from TJA1145.

    Best regards

    Ming

  • Hi ming:

         “2. In the case of the loopback disabled, when the first MIBSPI_transfer() is executed, the TX data buffer goes to TJA1145, the RX data buffer is the whatever sent from TJA1145 (it could be garbage this time). The TX and RX data buffers should be different, unless you did the external loopback on TJA1145. Do you know what data are expecting from the TJA1145? If yes, the RX data buffer should match with the expected data from TJA1145.”

         the the picture I provide as you see,there all the case  the loopback disabled。logic analyzer show rx an tx data is different and right 。but xds1100 show the sram is 0xffff。can you try it on your air board。
    Best regards

    ZDD

  • Hi ZDD,

    Since you are using the DMA mode, so please do CacheP_wbInv(gMibspiRxBuffer, APP_MIBSPI_MSGSIZE, CacheP_TYPE_ALLD) after the MIBSPI_transfer(), but before the data comparison.

    Best regards,

    Ming  

  • Hi ming:

         demo do not changed the part of  CacheP_wbInv,you mean loopback disabled or enable ,need change the part of  CacheP_wbInv?

         Best regards

         ZDD

  • Typo in previous reply. Is should be CacheP_inv(gMibspiRxBuffer, APP_MIBSPI_MSGSIZE, CacheP_TYPE_ALLD) after the MIBSPI_transfer(), but before the data comparison.