Tool/software:
Hi,
I initliazed EMAC using EMACHWInit api provided by HalCoGen however, after I write call EMACTransmit function, I don't see the transmission getting triggered. I checked the Tx0HDR after writing the base address of the dma descriptor and it stays as it is after write and never returns to zero indicating some issue with initliazation maybe? Any helpful pointers will be appreciated.
Thansk,
Ravi
Hi Jagadish,
Can you elaborate a bit more on what you meant by NORMAL_OINC_SHARED will not prevent caching? In HalCoGen, when I hover the cursor over NORMAL_OINC_SHARED , it says it marks the memory region as non cacheable and shared between bus masters (CPU and EMAC DMA in this case). I have attached the screenshot of this.
I tried your suggestion of marking the memory region as NORMAL_OIWTNOWA_SHARED but even that doesnt seem to help. The only way it works is if I disable cache completely.
Ravi
Hi Ravi,
Apologies for the late reply, i was stuck with some other issues as well in this mean time.
I found the root cause for the issue why write-through didn't work, the reason is i think you only configured write-through to the RAM region only.
But we should also need to configure write through to the descriptor memory as well.
So please try with below configuration, and verify:
This configuration worked at my end and i was able to get the RX ISR even if the cache is enabled.
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Thanks & regards,
Jagadish.
Hi Ravi,
I am talking about the below EMAC RAM area
This is the area where transmit and receive buffer descriptors will be stored right, i mean DMA will read this descriptor and will do the necessary transfers on data after calling the EMACTransmit function.
So, i thought you didn't configure this area into the WT (Write through) and you only configured the WT to the RAM area where the data will be stored.
Today i again tested with below configuration
Here i configured WT to the only RAM area where the data will be stored and still i got the receive interrupt.
I tried your suggestion of marking the memory region as NORMAL_OIWTNOWA_SHARED but even that doesnt seem to help. The only way it works is if I disable cache completely.
Just now i also tried this configuration as well with cache-enable and it worked (i got the receiving interrupt)
Now i don't understand why this failed on your end? did you configure as like i did?
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Thanks & regards,
Jagadish.
Hi Ravi,
That could be happen! Because if you verify the definition of EMACTransmit function we won't do any polling for data transfer, instead of we will just assign the EMAC buffer descriptors with the input data that needs to be send and we will come out of this function.
So that means the complete data transfer will not happen right in this function or just after this function. The transfer will take place in the background. Even you can call another EMACTransmit function before the previous transfer complete and if we do so the data won't get lost instead of the input data is assigned to some other buffer descriptors right after the previous buffer descriptors and in the background data transfer takes place.
So, this is the reason you didn't hit the breakpoint in the rx handler after you are setting the breakpoint right after the EMACTransmit function.
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Thanks & regards,
Jagadish.
Hi Ravi,
I placed an infinite while loop after the first transmit call and I still see that issue.
I don't see any such issue at my end.
As you can see in below picture, i also kept an infinite loop after the first transmission,
And you can see that EMAC Rx interrupt is still received.
And here is my code for your reference:
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Thanks & regards,
Jagadish.
