MCU-PLUS-SDK-AM243X: MMR write protection mechanisms

Hello Jimmy,

Can you please explain more details about  your requirements ?

MMR registers have lock and unlock support before writing any values to them and these registers have dedicated keys to lock and unlock.

If you look at the TRM you will get details about MMR protection registers.

5.1.1.3.1.2 Kick Protection Registers

Regards,

Anil.

Hi Anil.

Thank you for your response.

I noticed that in the security manual, MMR has two fault avoidance measures: Partition locks and MMR write protection mechanisms. There is an example provided for the Partition locks measure in the SDK. I am curious if there is also a similar example for the MMR write protection mechanisms measure, or could you provide a simple example program demonstrating its usage?

Best regards

Jimmy

Jimmy said:

could you provide a simple example program demonstrating its usage?

In any code that uses SYSCONFIG, you will see a function called Dpl_init() in ti_dpl_config.c. There you can see an example of protection for 'RTI0_CLK_SRC_SEL' where the SOC_controlModuleUnlockMMR() and SOC_controlModuleLockMMR() API is used:

void Dpl_init(void)
{
    /* initialize Hwi but keep interrupts disabled */
    HwiP_init();

    /* init debug log zones early */
    /* Debug log init */
    DebugP_logZoneEnable(DebugP_LOG_ZONE_ERROR);
    DebugP_logZoneEnable(DebugP_LOG_ZONE_WARN);
    /* UART console to use for reading input */
    DebugP_uartSetDrvIndex(CONFIG_UART0);


    /* set timer clock source */
    SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MAIN, MSS_RCM_PARTITION0);
    *(volatile uint32_t*)(RTI0_CLOCK_SRC_MUX_ADDR) = RTI0_CLOCK_SRC_WUCPUCLK;
    SOC_controlModuleLockMMR(SOC_DOMAIN_ID_MAIN, MSS_RCM_PARTITION0);
    /* initialize Clock */
    ClockP_init();



    /* Enable interrupt handling */
    HwiP_enable();
}

Hi Kier

Thank you for your response.

I understand the example you mentioned, but I believe it only implements MMR-F2: Partition locks mechanism, not MMR-F3: MMR write protection mechanisms.

As explained in the security manual:

6.3.107 MMR write protection mechanisms
This MMR module has Proxy Addressing enabled. Each of the following register descriptions lists the Proxy0 address offset which is intended as the normal read/write access address. A second Proxy1 address also exists to provide exclusive register write control to safety-aware processing elements. When the associated claim register bit is set, a register becomes read-only at its Proxy0 address and may only be written through its Proxy1 address. Claim registers themselves

According to your reply, there is no need for additional handling of MMR-F3: MMR write protection mechanisms; using SOC_controlModuleLockMMR and SOC_controlModuleUnlockMMR should suffice to implement the MMR-F3 measure. Am I interpreting this correctly?

Best regards

Jimmy

I don't have the security manual so perhaps this is best answered by TI.

Hi Anil.

Please follow up on this issue, thank you.

Best regards.

Jimmy

Hello Jimmy,

Jimmy said:

I understand the example you mentioned, but I believe it only implements MMR-F2: Partition locks mechanism, not MMR-F3: MMR write protection mechanisms.

Actually, I can say that the above code belongs to write  protection only.

If you look at the code, first we unlock the memory region and write data to the corresponding register and next lock the memory region.

So, here users can't write in to register after locking the memory region . That's why I am saying this method is write protection only.

I am not familiar to MMR - F3 implementation and moving to different expert to comment on the above issue ..

Sorry for delayed replies .

Regards,

Anil.

Hi Anil.

Thank you for your response. I will continue to wait for the results from other experts.

Best regards.

Jimmy

Hi Krithika

Thank you for your response, I have understood that MMR-F3 is guaranteed by hardware and does not require software operation.

Best regards.

Jimmy